/usr/src/linux-headers-5.15.0-181/arch/nds32/include/asm
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assembler.h5980644editdlrm
barrier.h4310644editdlrm
bitfield.h471270644editdlrm
cache.h2760644editdlrm
cacheflush.h19860644editdlrm
cache_info.h3150644editdlrm
current.h3040644editdlrm
delay.h9380644editdlrm
elf.h60210644editdlrm
fixmap.h8310644editdlrm
fpu.h31950644editdlrm
fpuemu.h12720644editdlrm
ftrace.h11610644editdlrm
futex.h24830644editdlrm
highmem.h16240644editdlrm
io.h24740644editdlrm
irqflags.h8480644editdlrm
Kbuild1940644editdlrm
l2_cache.h47910644editdlrm
linkage.h2640644editdlrm
memory.h27130644editdlrm
mmu.h2130644editdlrm
mmu_context.h14090644editdlrm
nds32.h20180644editdlrm
nds32_fpu_inst.h25100644editdlrm
page.h15910644editdlrm
perf_event.h4450644editdlrm
pgalloc.h14190644editdlrm
pgtable.h116760644editdlrm
pmu.h133500644editdlrm
proc-fns.h16680644editdlrm
processor.h24050644editdlrm
ptrace.h16860644editdlrm
sfp-machine.h44630644editdlrm
shmparam.h4620644editdlrm
stacktrace.h8840644editdlrm
string.h4710644editdlrm
suspend.h2580644editdlrm
swab.h8100644editdlrm
syscall.h54960644editdlrm
syscalls.h5100644editdlrm
thread_info.h23900644editdlrm
tlb.h2490644editdlrm
tlbflush.h11440644editdlrm
uaccess.h82720644editdlrm
unistd.h1560644editdlrm
vdso.h4290644editdlrm
vdso_datapage.h11040644editdlrm
vdso_timer_info.h3570644editdlrm
vermagic.h2140644editdlrm
vmalloc.h930644editdlrm
Edit: /usr/src/linux-headers-5.15.0-181/arch/nds32/include/asm/highmem.h (1624B)
/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (C) 2005-2017 Andes Technology Corporation #ifndef _ASM_HIGHMEM_H #define _ASM_HIGHMEM_H #include #include /* * Right now we initialize only a single pte table. It can be extended * easily, subsequent pte tables have to be allocated in one physical * chunk of RAM. */ /* * Ordering is (from lower to higher memory addresses): * * high_memory * Persistent kmap area * PKMAP_BASE * fixed_addresses * FIXADDR_START * FIXADDR_TOP * Vmalloc area * VMALLOC_START * VMALLOC_END */ #define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK)) #define LAST_PKMAP PTRS_PER_PTE #define LAST_PKMAP_MASK (LAST_PKMAP - 1) #define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT) #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) static inline void flush_cache_kmaps(void) { cpu_dcache_wbinval_all(); } /* declarations for highmem.c */ extern unsigned long highstart_pfn, highend_pfn; extern pte_t *pkmap_page_table; extern void kmap_init(void); /* * FIXME: The below looks broken vs. a kmap_atomic() in task context which * is interupted and another kmap_atomic() happens in interrupt context. * But what do I know about nds32. -- tglx */ #define arch_kmap_local_post_map(vaddr, pteval) \ do { \ __nds32__tlbop_inv(vaddr); \ __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN); \ __nds32__tlbop_rwr(pteval); \ __nds32__isb(); \ } while (0) #define arch_kmap_local_pre_unmap(vaddr) \ do { \ __nds32__tlbop_inv(vaddr); \ __nds32__isb(); \ } while (0) #endif