FM / asm

/usr/src/linux-headers-5.15.0-181/arch/openrisc/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/openrisc/include/asm

Name	Size	Mode	Actions
bitops/	-	0755	rm
asm-offsets.h	35	0644	edit dl rm
atomic.h	3609	0644	edit dl rm
barrier.h	203	0644	edit dl rm
bitops.h	1326	0644	edit dl rm
cache.h	681	0644	edit dl rm
cacheflush.h	2204	0644	edit dl rm
cmpxchg.h	4056	0644	edit dl rm
cpuinfo.h	763	0644	edit dl rm
delay.h	463	0644	edit dl rm
elf.h	1860	0644	edit dl rm
fixmap.h	2596	0644	edit dl rm
futex.h	2293	0644	edit dl rm
io.h	833	0644	edit dl rm
irq.h	561	0644	edit dl rm
irqflags.h	659	0644	edit dl rm
Kbuild	238	0644	edit dl rm
linkage.h	557	0644	edit dl rm
mmu.h	521	0644	edit dl rm
mmu_context.h	1108	0644	edit dl rm
page.h	2288	0644	edit dl rm
pgalloc.h	1831	0644	edit dl rm
pgtable.h	12749	0644	edit dl rm
processor.h	2339	0644	edit dl rm
ptrace.h	3201	0644	edit dl rm
serial.h	928	0644	edit dl rm
setup.h	293	0644	edit dl rm
smp.h	822	0644	edit dl rm
spinlock.h	778	0644	edit dl rm
spinlock_types.h	188	0644	edit dl rm
spr.h	991	0644	edit dl rm
spr_defs.h	23252	0644	edit dl rm
string.h	324	0644	edit dl rm
syscall.h	1658	0644	edit dl rm
syscalls.h	969	0644	edit dl rm
thread_info.h	3787	0644	edit dl rm
time.h	627	0644	edit dl rm
timex.h	707	0644	edit dl rm
tlb.h	651	0644	edit dl rm
tlbflush.h	1844	0644	edit dl rm
uaccess.h	7985	0644	edit dl rm
unwinder.h	557	0644	edit dl rm
vmalloc.h	102	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/openrisc/include/asm/futex.h (2293B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_OPENRISC_FUTEX_H
#define __ASM_OPENRISC_FUTEX_H

#ifdef __KERNEL__

#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/errno.h>

#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
({								\
	__asm__ __volatile__ (					\
		"1:	l.lwa	%0, %2			\n"	\
			insn				"\n"	\
		"2:	l.swa	%2, %1			\n"	\
		"	l.bnf	1b			\n"	\
		"	 l.ori	%1, r0, 0		\n"	\
		"3:					\n"	\
		".section .fixup,\"ax\"			\n"	\
		"4:	l.j	3b			\n"	\
		"	 l.addi	%1, r0, %3		\n"	\
		".previous				\n"	\
		".section __ex_table,\"a\"		\n"	\
		".word	1b,4b,2b,4b			\n"	\
		".previous				\n"	\
		: "=&r" (oldval), "=&r" (ret), "+m" (*uaddr)	\
		: "i" (-EFAULT), "r" (oparg)			\
		: "cc", "memory"				\
		);						\
})

static inline int
arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
{
	int oldval = 0, ret;

if (!access_ok(uaddr, sizeof(u32)))
		return -EFAULT;

switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op("l.or %1,%4,%4", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ADD:
		__futex_atomic_op("l.add %1,%0,%4", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op("l.or %1,%0,%4", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op("l.and %1,%0,%4", ret, oldval, uaddr, ~oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op("l.xor %1,%0,%4", ret, oldval, uaddr, oparg);
		break;
	default:
		ret = -ENOSYS;
	}

if (!ret)
		*oval = oldval;

return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
			      u32 oldval, u32 newval)
{
	int ret = 0;
	u32 prev;

if (!access_ok(uaddr, sizeof(u32)))
		return -EFAULT;

__asm__ __volatile__ (				\
		"1:	l.lwa	%1, %2		\n"	\
		"	l.sfeq	%1, %3		\n"	\
		"	l.bnf	3f		\n"	\
		"	 l.nop			\n"	\
		"2:	l.swa	%2, %4		\n"	\
		"	l.bnf	1b		\n"	\
		"	 l.nop			\n"	\
		"3:				\n"	\
		".section .fixup,\"ax\"		\n"	\
		"4:	l.j	3b		\n"	\
		"	 l.addi	%0, r0, %5	\n"	\
		".previous			\n"	\
		".section __ex_table,\"a\"	\n"	\
		".word	1b,4b,2b,4b		\n"	\
		".previous			\n"	\
		: "+r" (ret), "=&r" (prev), "+m" (*uaddr) \
		: "r" (oldval), "r" (newval), "i" (-EFAULT) \
		: "cc",	"memory"			\
		);

*uval = prev;
	return ret;
}

#endif /* __KERNEL__ */

#endif /* __ASM_OPENRISC_FUTEX_H */

/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASM_OPENRISC_FUTEX_H #define __ASM_OPENRISC_FUTEX_H #ifdef __KERNEL__ #include #include #include #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ ({ \ __asm__ __volatile__ ( \ "1: l.lwa %0, %2 \n" \ insn "\n" \ "2: l.swa %2, %1 \n" \ " l.bnf 1b \n" \ " l.ori %1, r0, 0 \n" \ "3: \n" \ ".section .fixup,\"ax\" \n" \ "4: l.j 3b \n" \ " l.addi %1, r0, %3 \n" \ ".previous \n" \ ".section __ex_table,\"a\" \n" \ ".word 1b,4b,2b,4b \n" \ ".previous \n" \ : "=&r" (oldval), "=&r" (ret), "+m" (*uaddr) \ : "i" (-EFAULT), "r" (oparg) \ : "cc", "memory" \ ); \ }) static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) { int oldval = 0, ret; if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; switch (op) { case FUTEX_OP_SET: __futex_atomic_op("l.or %1,%4,%4", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ADD: __futex_atomic_op("l.add %1,%0,%4", ret, oldval, uaddr, oparg); break; case FUTEX_OP_OR: __futex_atomic_op("l.or %1,%0,%4", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ANDN: __futex_atomic_op("l.and %1,%0,%4", ret, oldval, uaddr, ~oparg); break; case FUTEX_OP_XOR: __futex_atomic_op("l.xor %1,%0,%4", ret, oldval, uaddr, oparg); break; default: ret = -ENOSYS; } if (!ret) *oval = oldval; return ret; } static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval) { int ret = 0; u32 prev; if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; __asm__ __volatile__ ( \ "1: l.lwa %1, %2 \n" \ " l.sfeq %1, %3 \n" \ " l.bnf 3f \n" \ " l.nop \n" \ "2: l.swa %2, %4 \n" \ " l.bnf 1b \n" \ " l.nop \n" \ "3: \n" \ ".section .fixup,\"ax\" \n" \ "4: l.j 3b \n" \ " l.addi %0, r0, %5 \n" \ ".previous \n" \ ".section __ex_table,\"a\" \n" \ ".word 1b,4b,2b,4b \n" \ ".previous \n" \ : "+r" (ret), "=&r" (prev), "+m" (*uaddr) \ : "r" (oldval), "r" (newval), "i" (-EFAULT) \ : "cc", "memory" \ ); *uval = prev; return ret; } #endif /* __KERNEL__ */ #endif /* __ASM_OPENRISC_FUTEX_H */