FM / asm

/usr/src/linux-headers-5.15.0-181/arch/riscv/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/riscv/include/asm

Name	Size	Mode	Actions
vdso/	-	0755	rm
alternative-macros.h	4658	0644	edit dl rm
alternative.h	930	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	1040	0644	edit dl rm
asm.h	1558	0644	edit dl rm
atomic.h	11028	0644	edit dl rm
barrier.h	2458	0644	edit dl rm
bitops.h	5809	0644	edit dl rm
bug.h	2186	0644	edit dl rm
cache.h	516	0644	edit dl rm
cacheflush.h	1307	0644	edit dl rm
cacheinfo.h	511	0644	edit dl rm
clint.h	797	0644	edit dl rm
clocksource.h	136	0644	edit dl rm
cmpxchg.h	9537	0644	edit dl rm
cpu_ops.h	1494	0644	edit dl rm
csr.h	6062	0644	edit dl rm
current.h	940	0644	edit dl rm
delay.h	471	0644	edit dl rm
efi.h	1150	0644	edit dl rm
elf.h	2726	0644	edit dl rm
errata_list.h	1074	0644	edit dl rm
fence.h	279	0644	edit dl rm
fixmap.h	1806	0644	edit dl rm
ftrace.h	3086	0644	edit dl rm
futex.h	2906	0644	edit dl rm
gdb_xml.h	5601	0644	edit dl rm
hugetlb.h	360	0644	edit dl rm
hwcap.h	1245	0644	edit dl rm
image.h	1673	0644	edit dl rm
io.h	5322	0644	edit dl rm
irq.h	347	0644	edit dl rm
irqflags.h	1175	0644	edit dl rm
irq_work.h	225	0644	edit dl rm
jump_label.h	1440	0644	edit dl rm
kasan.h	1390	0644	edit dl rm
Kbuild	178	0644	edit dl rm
kdebug.h	158	0644	edit dl rm
kexec.h	1349	0644	edit dl rm
kfence.h	1312	0644	edit dl rm
kgdb.h	2494	0644	edit dl rm
kprobes.h	1136	0644	edit dl rm
linkage.h	267	0644	edit dl rm
mmio.h	5347	0644	edit dl rm
mmiowb.h	398	0644	edit dl rm
mmu.h	610	0644	edit dl rm
mmu_context.h	898	0644	edit dl rm
mmzone.h	266	0644	edit dl rm
module.h	2984	0644	edit dl rm
module.lds.h	207	0644	edit dl rm
numa.h	165	0644	edit dl rm
page.h	5264	0644	edit dl rm
parse_asm.h	7265	0644	edit dl rm
patch.h	314	0644	edit dl rm
pci.h	1062	0644	edit dl rm
perf_event.h	2204	0644	edit dl rm
pgalloc.h	1801	0644	edit dl rm
pgtable-32.h	498	0644	edit dl rm
pgtable-64.h	1898	0644	edit dl rm
pgtable-bits.h	1552	0644	edit dl rm
pgtable.h	18086	0644	edit dl rm
probes.h	563	0644	edit dl rm
processor.h	2138	0644	edit dl rm
ptdump.h	338	0644	edit dl rm
ptrace.h	4304	0644	edit dl rm
sbi.h	4223	0644	edit dl rm
seccomp.h	504	0644	edit dl rm
sections.h	883	0644	edit dl rm
set_memory.h	1869	0644	edit dl rm
smp.h	2427	0644	edit dl rm
soc.h	627	0644	edit dl rm
sparsemem.h	263	0644	edit dl rm
spinlock.h	2508	0644	edit dl rm
spinlock_types.h	530	0644	edit dl rm
stackprotector.h	768	0644	edit dl rm
stacktrace.h	496	0644	edit dl rm
string.h	1078	0644	edit dl rm
switch_to.h	2107	0644	edit dl rm
syscall.h	2163	0644	edit dl rm
thread_info.h	3955	0644	edit dl rm
timex.h	1859	0644	edit dl rm
tlb.h	403	0644	edit dl rm
tlbflush.h	1803	0644	edit dl rm
uaccess.h	13955	0644	edit dl rm
unistd.h	328	0644	edit dl rm
uprobes.h	828	0644	edit dl rm
vdso.h	868	0644	edit dl rm
vendorid_list.h	172	0644	edit dl rm
vermagic.h	213	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm
word-at-a-time.h	1104	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/riscv/include/asm/gdb_xml.h (5601B)

/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __ASM_GDB_XML_H_
#define __ASM_GDB_XML_H_

const char riscv_gdb_stub_feature[64] =
			"PacketSize=800;qXfer:features:read+;";

static const char gdb_xfer_read_target[31] = "qXfer:features:read:target.xml:";

#ifdef CONFIG_64BIT
static const char gdb_xfer_read_cpuxml[39] =
			"qXfer:features:read:riscv-64bit-cpu.xml";

static const char riscv_gdb_stub_target_desc[256] =
"l<?xml version=\"1.0\"?>"
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target>"
"<xi:include href=\"riscv-64bit-cpu.xml\"/>"
"</target>";

static const char riscv_gdb_stub_cpuxml[2048] =
"l<?xml version=\"1.0\"?>"
"<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
"<feature name=\"org.gnu.gdb.riscv.cpu\">"
"<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
"<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
"<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_TP"\" bitsize=\"64\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_T0"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_T1"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_T2"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_FP"\" bitsize=\"64\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_S1"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A0"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A1"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A2"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A3"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A4"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A5"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A6"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_A7"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S2"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S3"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S4"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S5"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S6"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S7"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S8"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S9"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S10"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_S11"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_T3"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_T4"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_T5"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_T6"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_EPC"\" bitsize=\"64\" type=\"code_ptr\"/>"
"<reg name=\""DBG_REG_STATUS"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_BADADDR"\" bitsize=\"64\" type=\"int\"/>"
"<reg name=\""DBG_REG_CAUSE"\" bitsize=\"64\" type=\"int\"/>"
"</feature>";
#else
static const char gdb_xfer_read_cpuxml[39] =
			"qXfer:features:read:riscv-32bit-cpu.xml";

static const char riscv_gdb_stub_target_desc[256] =
"l<?xml version=\"1.0\"?>"
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target>"
"<xi:include href=\"riscv-32bit-cpu.xml\"/>"
"</target>";

static const char riscv_gdb_stub_cpuxml[2048] =
"l<?xml version=\"1.0\"?>"
"<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
"<feature name=\"org.gnu.gdb.riscv.cpu\">"
"<reg name=\""DBG_REG_ZERO"\" bitsize=\"32\" type=\"int\" regnum=\"0\"/>"
"<reg name=\""DBG_REG_RA"\" bitsize=\"32\" type=\"code_ptr\"/>"
"<reg name=\""DBG_REG_SP"\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_GP"\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_TP"\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_T0"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_T1"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_T2"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_FP"\" bitsize=\"32\" type=\"data_ptr\"/>"
"<reg name=\""DBG_REG_S1"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A0"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A1"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A2"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A3"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A4"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A5"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A6"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_A7"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S2"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S3"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S4"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S5"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S6"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S7"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S8"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S9"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S10"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_S11"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_T3"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_T4"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_T5"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_T6"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_EPC"\" bitsize=\"32\" type=\"code_ptr\"/>"
"<reg name=\""DBG_REG_STATUS"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_BADADDR"\" bitsize=\"32\" type=\"int\"/>"
"<reg name=\""DBG_REG_CAUSE"\" bitsize=\"32\" type=\"int\"/>"
"</feature>";
#endif
#endif

/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __ASM_GDB_XML_H_ #define __ASM_GDB_XML_H_ const char riscv_gdb_stub_feature[64] = "PacketSize=800;qXfer:features:read+;"; static const char gdb_xfer_read_target[31] = "qXfer:features:read:target.xml:"; #ifdef CONFIG_64BIT static const char gdb_xfer_read_cpuxml[39] = "qXfer:features:read:riscv-64bit-cpu.xml"; static const char riscv_gdb_stub_target_desc[256] = "l" "" "" "" ""; static const char riscv_gdb_stub_cpuxml[2048] = "l" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" ""; #else static const char gdb_xfer_read_cpuxml[39] = "qXfer:features:read:riscv-32bit-cpu.xml"; static const char riscv_gdb_stub_target_desc[256] = "l" "" "" "" ""; static const char riscv_gdb_stub_cpuxml[2048] = "l" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" ""; #endif #endif