/usr/src/linux-headers-5.15.0-181/arch/xtensa/include/asm/
/usr/src/linux-headers-5.15.0-181/arch/xtensa/include/asm
NameSizeModeActions
asm-offsets.h350644editdlrm
asm-uaccess.h41800644editdlrm
asmmacro.h47630644editdlrm
atomic.h73010644editdlrm
barrier.h5940644editdlrm
bitops.h53980644editdlrm
bootparam.h14020644editdlrm
cache.h11140644editdlrm
cacheasm.h38560644editdlrm
cacheflush.h59680644editdlrm
checksum.h58930644editdlrm
cmpxchg.h56840644editdlrm
coprocessor.h46230644editdlrm
core.h8300644editdlrm
current.h6790644editdlrm
delay.h16680644editdlrm
dma.h18300644editdlrm
elf.h51150644editdlrm
fixmap.h11060644editdlrm
flat.h4400644editdlrm
ftrace.h9790644editdlrm
futex.h38890644editdlrm
highmem.h21670644editdlrm
hw_breakpoint.h15970644editdlrm
initialize_mmu.h51960644editdlrm
io.h19590644editdlrm
irq.h11270644editdlrm
irqflags.h20690644editdlrm
jump_label.h16550644editdlrm
kasan.h8590644editdlrm
Kbuild2300644editdlrm
kmem_layout.h27900644editdlrm
linkage.h1540644editdlrm
mmu.h4620644editdlrm
mmu_context.h36240644editdlrm
mxregs.h13300644editdlrm
nommu_context.h1560644editdlrm
page.h57930644editdlrm
pci-bridge.h21700644editdlrm
pci.h13020644editdlrm
perf_event.h1080644editdlrm
pgalloc.h14050644editdlrm
pgtable.h144700644editdlrm
platform.h15280644editdlrm
processor.h77050644editdlrm
ptrace.h33210644editdlrm
regs.h40170644editdlrm
seccomp.h2870644editdlrm
serial.h4430644editdlrm
shmparam.h5610644editdlrm
signal.h5020644editdlrm
smp.h9670644editdlrm
spinlock.h4720644editdlrm
spinlock_types.h3170644editdlrm
stackprotector.h11400644editdlrm
stacktrace.h11580644editdlrm
string.h33850644editdlrm
switch_to.h6010644editdlrm
syscall.h21400644editdlrm
sysmem.h4260644editdlrm
thread_info.h39650644editdlrm
timex.h14400644editdlrm
tlb.h4750644editdlrm
tlbflush.h56200644editdlrm
traps.h27790644editdlrm
uaccess.h93750644editdlrm
ucontext.h5400644editdlrm
unistd.h3700644editdlrm
vectors.h32760644editdlrm
vermagic.h4330644editdlrm
vmalloc.h960644editdlrm
Edit: /usr/src/linux-headers-5.15.0-181/arch/xtensa/include/asm/cacheasm.h (3856B)
/* * include/asm-xtensa/cacheasm.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2006 Tensilica Inc. */ #include #include #include /* * Define cache functions as macros here so that they can be used * by the kernel and boot loader. We should consider moving them to a * library that can be linked by both. * * Locking * * ___unlock_dcache_all * ___unlock_icache_all * * Flush and invaldating * * ___flush_invalidate_dcache_{all|range|page} * ___flush_dcache_{all|range|page} * ___invalidate_dcache_{all|range|page} * ___invalidate_icache_{all|range|page} * */ .macro __loop_cache_unroll ar at insn size line_width max_immed .if (1 << (\line_width)) > (\max_immed) .set _reps, 1 .elseif (2 << (\line_width)) > (\max_immed) .set _reps, 2 .else .set _reps, 4 .endif __loopi \ar, \at, \size, (_reps << (\line_width)) .set _index, 0 .rep _reps \insn \ar, _index << (\line_width) .set _index, _index + 1 .endr __endla \ar, \at, _reps << (\line_width) .endm .macro __loop_cache_all ar at insn size line_width max_immed movi \ar, 0 __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed .endm .macro __loop_cache_range ar as at insn line_width extui \at, \ar, 0, \line_width add \as, \as, \at __loops \ar, \as, \at, \line_width \insn \ar, 0 __endla \ar, \at, (1 << (\line_width)) .endm .macro __loop_cache_page ar at insn line_width max_immed __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed .endm .macro ___unlock_dcache_all ar at #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 240 #endif .endm .macro ___unlock_icache_all ar at #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \ XCHAL_ICACHE_LINEWIDTH 240 #endif .endm .macro ___flush_invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 240 #endif .endm .macro ___flush_dcache_all ar at #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 240 #endif .endm .macro ___invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \ XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___invalidate_icache_all ar at #if XCHAL_ICACHE_SIZE __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \ XCHAL_ICACHE_LINEWIDTH 1020 #endif .endm .macro ___flush_invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH #endif .endm .macro ___flush_dcache_range ar as at #if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH #endif .endm .macro ___invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH #endif .endm .macro ___invalidate_icache_range ar as at #if XCHAL_ICACHE_SIZE __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH #endif .endm .macro ___flush_invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___flush_dcache_page ar as #if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020 #endif .endm .macro ___invalidate_icache_page ar as #if XCHAL_ICACHE_SIZE __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020 #endif .endm