/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/
/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm
NameSizeModeActions
assembler.h5980644editdlrm
barrier.h4310644editdlrm
bitfield.h471270644editdlrm
cache.h2760644editdlrm
cacheflush.h19860644editdlrm
cache_info.h3150644editdlrm
current.h3040644editdlrm
delay.h9380644editdlrm
elf.h60210644editdlrm
fixmap.h8310644editdlrm
fpu.h31950644editdlrm
fpuemu.h12720644editdlrm
ftrace.h11610644editdlrm
futex.h24830644editdlrm
highmem.h16240644editdlrm
io.h24740644editdlrm
irqflags.h8480644editdlrm
Kbuild1940644editdlrm
l2_cache.h47910644editdlrm
linkage.h2640644editdlrm
memory.h27130644editdlrm
mmu.h2130644editdlrm
mmu_context.h14090644editdlrm
nds32.h20180644editdlrm
nds32_fpu_inst.h25100644editdlrm
page.h15910644editdlrm
perf_event.h4450644editdlrm
pgalloc.h14190644editdlrm
pgtable.h116760644editdlrm
pmu.h133500644editdlrm
proc-fns.h16680644editdlrm
processor.h24050644editdlrm
ptrace.h16860644editdlrm
sfp-machine.h44630644editdlrm
shmparam.h4620644editdlrm
stacktrace.h8840644editdlrm
string.h4710644editdlrm
suspend.h2580644editdlrm
swab.h8100644editdlrm
syscall.h54960644editdlrm
syscalls.h5100644editdlrm
thread_info.h23900644editdlrm
tlb.h2490644editdlrm
tlbflush.h11440644editdlrm
uaccess.h82720644editdlrm
unistd.h1560644editdlrm
vdso.h4290644editdlrm
vdso_datapage.h11040644editdlrm
vdso_timer_info.h3570644editdlrm
vermagic.h2140644editdlrm
vmalloc.h930644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/bitfield.h (47127B)
/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (C) 2005-2017 Andes Technology Corporation #ifndef __NDS32_BITFIELD_H__ #define __NDS32_BITFIELD_H__ /****************************************************************************** * cr0: CPU_VER (CPU Version Register) *****************************************************************************/ #define CPU_VER_offCFGID 0 /* Minor configuration */ #define CPU_VER_offREV 16 /* Revision of the CPU version */ #define CPU_VER_offCPUID 24 /* Major CPU versions */ #define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID ) #define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV ) #define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID ) /****************************************************************************** * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register) *****************************************************************************/ #define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */ #define ICM_CFG_offIWAY 3 /* I-cache ways */ #define ICM_CFG_offISZ 6 /* I-cache line size */ #define ICM_CFG_offILCK 9 /* I-cache locking support */ #define ICM_CFG_offILMB 10 /* On-chip ILM banks */ #define ICM_CFG_offBSAV 13 /* ILM base register alignment version */ /* bit 15:31 reserved */ #define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET ) #define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY ) #define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ ) #define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK ) #define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB ) #define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV ) /****************************************************************************** * cr2: DCM_CFG (Data Cache/Memory Configuration Register) *****************************************************************************/ #define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */ #define DCM_CFG_offDWAY 3 /* D-cache ways */ #define DCM_CFG_offDSZ 6 /* D-cache line size */ #define DCM_CFG_offDLCK 9 /* D-cache locking support */ #define DCM_CFG_offDLMB 10 /* On-chip DLM banks */ #define DCM_CFG_offBSAV 13 /* DLM base register alignment version */ /* bit 15:31 reserved */ #define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET ) #define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY ) #define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ ) #define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK ) #define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB ) #define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV ) /****************************************************************************** * cr3: MMU_CFG (MMU Configuration Register) *****************************************************************************/ #define MMU_CFG_offMMPS 0 /* Memory management protection scheme */ #define MMU_CFG_offMMPV 2 /* Memory management protection version number */ #define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */ #define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */ #define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */ /* bit 14:14 reserved */ #define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */ #define MMU_CFG_offfEPSZ 16 /* Extra page size supported */ #define MMU_CFG_offTLBLCK 24 /* TLB locking support */ #define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */ #define MMU_CFG_offDE 26 /* Default endian */ #define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */ #define MMU_CFG_offIVTB 28 /* Invisible TLB */ #define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */ #define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */ /* bit 31 reserved */ #define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS ) #define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV ) #define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB ) #define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW ) #define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS ) #define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 ) #define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ ) #define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK ) #define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK ) #define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE ) #define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT ) #define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB ) #define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT ) #define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME ) /****************************************************************************** * cr4: MSC_CFG (Misc Configuration Register) *****************************************************************************/ #define MSC_CFG_offEDM 0 #define MSC_CFG_offLMDMA 1 #define MSC_CFG_offPFM 2 #define MSC_CFG_offHSMP 3 #define MSC_CFG_offTRACE 4 #define MSC_CFG_offDIV 5 #define MSC_CFG_offMAC 6 #define MSC_CFG_offAUDIO 7 #define MSC_CFG_offL2C 9 #define MSC_CFG_offRDREG 10 #define MSC_CFG_offADR24 11 #define MSC_CFG_offINTLC 12 #define MSC_CFG_offBASEV 13 #define MSC_CFG_offNOD 16 /* bit 13:31 reserved */ #define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM ) #define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA ) #define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM ) #define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP ) #define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE ) #define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV ) #define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC ) #define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO ) #define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C ) #define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG ) #define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 ) #define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC ) #define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV ) #define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD ) /****************************************************************************** * cr5: CORE_CFG (Core Identification Register) *****************************************************************************/ #define CORE_ID_offCOREID 0 /* bit 4:31 reserved */ #define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID ) /****************************************************************************** * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register) *****************************************************************************/ #define FUCOP_EXIST_offCP0EX 0 #define FUCOP_EXIST_offCP1EX 1 #define FUCOP_EXIST_offCP2EX 2 #define FUCOP_EXIST_offCP3EX 3 #define FUCOP_EXIST_offCP0ISFPU 31 #define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX ) #define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX ) #define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX ) #define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX ) #define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU ) /****************************************************************************** * ir0: PSW (Processor Status Word Register) * ir1: IPSW (Interruption PSW Register) * ir2: P_IPSW (Previous IPSW Register) *****************************************************************************/ #define PSW_offGIE 0 /* Global Interrupt Enable */ #define PSW_offINTL 1 /* Interruption Stack Level */ #define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */ #define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */ #define PSW_offIT 6 /* Enable instruction address translation */ #define PSW_offDT 7 /* Enable data address translation */ #define PSW_offIME 8 /* Instruction Machine Error flag */ #define PSW_offDME 9 /* Data Machine Error flag */ #define PSW_offDEX 10 /* Debug Exception */ #define PSW_offHSS 11 /* Hardware Single Stepping */ #define PSW_offDRBE 12 /* Device Register Endian Mode */ #define PSW_offAEN 13 /* Audio ISA special feature */ #define PSW_offWBNA 14 /* Write Back Non-Allocate */ #define PSW_offIFCON 15 /* IFC On */ #define PSW_offCPL 16 /* Current Priority Level */ /* bit 19:31 reserved */ #define PSW_mskGIE ( 0x1 << PSW_offGIE ) #define PSW_mskINTL ( 0x3 << PSW_offINTL ) #define PSW_mskPOM ( 0x3 << PSW_offPOM ) #define PSW_mskBE ( 0x1 << PSW_offBE ) #define PSW_mskIT ( 0x1 << PSW_offIT ) #define PSW_mskDT ( 0x1 << PSW_offDT ) #define PSW_mskIME ( 0x1 << PSW_offIME ) #define PSW_mskDME ( 0x1 << PSW_offDME ) #define PSW_mskDEX ( 0x1 << PSW_offDEX ) #define PSW_mskHSS ( 0x1 << PSW_offHSS ) #define PSW_mskDRBE ( 0x1 << PSW_offDRBE ) #define PSW_mskAEN ( 0x1 << PSW_offAEN ) #define PSW_mskWBNA ( 0x1 << PSW_offWBNA ) #define PSW_mskIFCON ( 0x1 << PSW_offIFCON ) #define PSW_mskCPL ( 0x7 << PSW_offCPL ) #define PSW_SYSTEM ( 1 << PSW_offPOM ) #define PSW_INTL_1 ( 1 << PSW_offINTL ) #define PSW_CPL_NO ( 0 << PSW_offCPL ) #define PSW_CPL_ANY ( 7 << PSW_offCPL ) #define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA) #ifdef __NDS32_EB__ #ifdef CONFIG_WBNA #define PSW_init (PSW_mskWBNA|(1<