/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm
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assembler.h5980644editdlrm
barrier.h4310644editdlrm
bitfield.h471270644editdlrm
cache.h2760644editdlrm
cacheflush.h19860644editdlrm
cache_info.h3150644editdlrm
current.h3040644editdlrm
delay.h9380644editdlrm
elf.h60210644editdlrm
fixmap.h8310644editdlrm
fpu.h31950644editdlrm
fpuemu.h12720644editdlrm
ftrace.h11610644editdlrm
futex.h24830644editdlrm
highmem.h16240644editdlrm
io.h24740644editdlrm
irqflags.h8480644editdlrm
Kbuild1940644editdlrm
l2_cache.h47910644editdlrm
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memory.h27130644editdlrm
mmu.h2130644editdlrm
mmu_context.h14090644editdlrm
nds32.h20180644editdlrm
nds32_fpu_inst.h25100644editdlrm
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pgalloc.h14190644editdlrm
pgtable.h116760644editdlrm
pmu.h133500644editdlrm
proc-fns.h16680644editdlrm
processor.h24050644editdlrm
ptrace.h16860644editdlrm
sfp-machine.h44630644editdlrm
shmparam.h4620644editdlrm
stacktrace.h8840644editdlrm
string.h4710644editdlrm
suspend.h2580644editdlrm
swab.h8100644editdlrm
syscall.h54960644editdlrm
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thread_info.h23900644editdlrm
tlb.h2490644editdlrm
tlbflush.h11440644editdlrm
uaccess.h82720644editdlrm
unistd.h1560644editdlrm
vdso.h4290644editdlrm
vdso_datapage.h11040644editdlrm
vdso_timer_info.h3570644editdlrm
vermagic.h2140644editdlrm
vmalloc.h930644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/futex.h (2483B)
/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (C) 2005-2017 Andes Technology Corporation #ifndef __NDS32_FUTEX_H__ #define __NDS32_FUTEX_H__ #include #include #include #define __futex_atomic_ex_table(err_reg) \ " .pushsection __ex_table,\"a\"\n" \ " .align 3\n" \ " .long 1b, 4f\n" \ " .long 2b, 4f\n" \ " .popsection\n" \ " .pushsection .fixup,\"ax\"\n" \ "4: move %0, " err_reg "\n" \ " b 3b\n" \ " .popsection" #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ smp_mb(); \ asm volatile( \ " movi $ta, #0\n" \ "1: llw %1, [%2+$ta]\n" \ " " insn "\n" \ "2: scw %0, [%2+$ta]\n" \ " beqz %0, 1b\n" \ " movi %0, #0\n" \ "3:\n" \ __futex_atomic_ex_table("%4") \ : "=&r" (ret), "=&r" (oldval) \ : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \ : "cc", "memory") static inline int futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr, u32 oldval, u32 newval) { int ret = 0; u32 val, tmp, flags; if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; smp_mb(); asm volatile (" movi $ta, #0\n" "1: llw %1, [%6 + $ta]\n" " sub %3, %1, %4\n" " cmovz %2, %5, %3\n" " cmovn %2, %1, %3\n" "2: scw %2, [%6 + $ta]\n" " beqz %2, 1b\n" "3:\n " __futex_atomic_ex_table("%7") :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags) :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT) :"$ta", "memory"); smp_mb(); *uval = val; return ret; } static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) { int oldval = 0, ret; if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; switch (op) { case FUTEX_OP_SET: __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr, oparg); break; case FUTEX_OP_ADD: __futex_atomic_op("add %0, %1, %3", ret, oldval, tmp, uaddr, oparg); break; case FUTEX_OP_OR: __futex_atomic_op("or %0, %1, %3", ret, oldval, tmp, uaddr, oparg); break; case FUTEX_OP_ANDN: __futex_atomic_op("and %0, %1, %3", ret, oldval, tmp, uaddr, ~oparg); break; case FUTEX_OP_XOR: __futex_atomic_op("xor %0, %1, %3", ret, oldval, tmp, uaddr, oparg); break; default: ret = -ENOSYS; } if (!ret) *oval = oldval; return ret; } #endif /* __NDS32_FUTEX_H__ */