/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm
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assembler.h5980644editdlrm
barrier.h4310644editdlrm
bitfield.h471270644editdlrm
cache.h2760644editdlrm
cacheflush.h19860644editdlrm
cache_info.h3150644editdlrm
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elf.h60210644editdlrm
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fpu.h31950644editdlrm
fpuemu.h12720644editdlrm
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highmem.h16240644editdlrm
io.h24740644editdlrm
irqflags.h8480644editdlrm
Kbuild1940644editdlrm
l2_cache.h47910644editdlrm
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memory.h27130644editdlrm
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mmu_context.h14090644editdlrm
nds32.h20180644editdlrm
nds32_fpu_inst.h25100644editdlrm
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vdso_datapage.h11040644editdlrm
vdso_timer_info.h3570644editdlrm
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vmalloc.h930644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/io.h (2474B)
/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (C) 2005-2017 Andes Technology Corporation #ifndef __ASM_NDS32_IO_H #define __ASM_NDS32_IO_H #include #define __raw_writeb __raw_writeb static inline void __raw_writeb(u8 val, volatile void __iomem *addr) { asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr)); } #define __raw_writew __raw_writew static inline void __raw_writew(u16 val, volatile void __iomem *addr) { asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr)); } #define __raw_writel __raw_writel static inline void __raw_writel(u32 val, volatile void __iomem *addr) { asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr)); } #define __raw_readb __raw_readb static inline u8 __raw_readb(const volatile void __iomem *addr) { u8 val; asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr)); return val; } #define __raw_readw __raw_readw static inline u16 __raw_readw(const volatile void __iomem *addr) { u16 val; asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr)); return val; } #define __raw_readl __raw_readl static inline u32 __raw_readl(const volatile void __iomem *addr) { u32 val; asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr)); return val; } #define __iormb() rmb() #define __iowmb() wmb() /* * {read,write}{b,w,l,q}_relaxed() are like the regular version, but * are not guaranteed to provide ordering against spinlocks or memory * accesses. */ #define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; }) #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; }) #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; }) #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) /* * {read,write}{b,w,l,q}() access little endian memory and return result in * native endianness. */ #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) #include #endif /* __ASM_NDS32_IO_H */