FM / asm

/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm

Name	Size	Mode	Actions
assembler.h	598	0644	edit dl rm
barrier.h	431	0644	edit dl rm
bitfield.h	47127	0644	edit dl rm
cache.h	276	0644	edit dl rm
cacheflush.h	1986	0644	edit dl rm
cache_info.h	315	0644	edit dl rm
current.h	304	0644	edit dl rm
delay.h	938	0644	edit dl rm
elf.h	6021	0644	edit dl rm
fixmap.h	831	0644	edit dl rm
fpu.h	3195	0644	edit dl rm
fpuemu.h	1272	0644	edit dl rm
ftrace.h	1161	0644	edit dl rm
futex.h	2483	0644	edit dl rm
highmem.h	1624	0644	edit dl rm
io.h	2474	0644	edit dl rm
irqflags.h	848	0644	edit dl rm
Kbuild	194	0644	edit dl rm
l2_cache.h	4791	0644	edit dl rm
linkage.h	264	0644	edit dl rm
memory.h	2713	0644	edit dl rm
mmu.h	213	0644	edit dl rm
mmu_context.h	1409	0644	edit dl rm
nds32.h	2018	0644	edit dl rm
nds32_fpu_inst.h	2510	0644	edit dl rm
page.h	1591	0644	edit dl rm
perf_event.h	445	0644	edit dl rm
pgalloc.h	1419	0644	edit dl rm
pgtable.h	11676	0644	edit dl rm
pmu.h	13350	0644	edit dl rm
proc-fns.h	1668	0644	edit dl rm
processor.h	2405	0644	edit dl rm
ptrace.h	1686	0644	edit dl rm
sfp-machine.h	4463	0644	edit dl rm
shmparam.h	462	0644	edit dl rm
stacktrace.h	884	0644	edit dl rm
string.h	471	0644	edit dl rm
suspend.h	258	0644	edit dl rm
swab.h	810	0644	edit dl rm
syscall.h	5496	0644	edit dl rm
syscalls.h	510	0644	edit dl rm
thread_info.h	2390	0644	edit dl rm
tlb.h	249	0644	edit dl rm
tlbflush.h	1144	0644	edit dl rm
uaccess.h	8272	0644	edit dl rm
unistd.h	156	0644	edit dl rm
vdso.h	429	0644	edit dl rm
vdso_datapage.h	1104	0644	edit dl rm
vdso_timer_info.h	357	0644	edit dl rm
vermagic.h	214	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/nds32.h (2018B)

/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (C) 2005-2017 Andes Technology Corporation

#ifndef _ASM_NDS32_NDS32_H_
#define _ASM_NDS32_NDS32_H_

#include <asm/bitfield.h>
#include <asm/cachectl.h>

#ifndef __ASSEMBLY__
#include <linux/init.h>
#include <asm/barrier.h>
#include <nds32_intrinsic.h>

#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
#define FP_OFFSET (-3)
#else
#define FP_OFFSET (-2)
#endif
#define LP_OFFSET (-1)

extern void __init early_trap_init(void);
static inline void GIE_ENABLE(void)
{
	mb();
	__nds32__gie_en();
}

static inline void GIE_DISABLE(void)
{
	mb();
	__nds32__gie_dis();
}

static inline unsigned long CACHE_SET(unsigned char cache)
{

if (cache == ICACHE)
		return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
			      ICM_CFG_offISET);
	else
		return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
			      DCM_CFG_offDSET);
}

static inline unsigned long CACHE_WAY(unsigned char cache)
{

if (cache == ICACHE)
		return 1 +
		    ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
	else
		return 1 +
		    ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
}

static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
{

if (cache == ICACHE)
		return 8 <<
		    (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
	else
		return 8 <<
		    (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
}

#endif /* __ASSEMBLY__ */

#define IVB_BASE		PHYS_OFFSET	/* in user space for intr/exc/trap/break table base, 64KB aligned
						 * We defined at the start of the physical memory */

/* dispatched sub-entry exception handler numbering */
#define RD_PROT			0	/* read protrection */
#define WRT_PROT		1	/* write protection */
#define NOEXEC			2	/* non executable */
#define PAGE_MODIFY		3	/* page modified */
#define ACC_BIT			4	/* access bit */
#define RESVED_PTE		5	/* reserved PTE attribute */
/* reserved 6 ~ 16 */

#endif /* _ASM_NDS32_NDS32_H_ */

/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (C) 2005-2017 Andes Technology Corporation #ifndef _ASM_NDS32_NDS32_H_ #define _ASM_NDS32_NDS32_H_ #include #include #ifndef __ASSEMBLY__ #include #include #include #ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE #define FP_OFFSET (-3) #else #define FP_OFFSET (-2) #endif #define LP_OFFSET (-1) extern void __init early_trap_init(void); static inline void GIE_ENABLE(void) { mb(); __nds32__gie_en(); } static inline void GIE_DISABLE(void) { mb(); __nds32__gie_dis(); } static inline unsigned long CACHE_SET(unsigned char cache) { if (cache == ICACHE) return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >> ICM_CFG_offISET); else return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >> DCM_CFG_offDSET); } static inline unsigned long CACHE_WAY(unsigned char cache) { if (cache == ICACHE) return 1 + ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY); else return 1 + ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY); } static inline unsigned long CACHE_LINE_SIZE(unsigned char cache) { if (cache == ICACHE) return 8 << (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1); else return 8 << (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1); } #endif /* __ASSEMBLY__ */ #define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned * We defined at the start of the physical memory */ /* dispatched sub-entry exception handler numbering */ #define RD_PROT 0 /* read protrection */ #define WRT_PROT 1 /* write protection */ #define NOEXEC 2 /* non executable */ #define PAGE_MODIFY 3 /* page modified */ #define ACC_BIT 4 /* access bit */ #define RESVED_PTE 5 /* reserved PTE attribute */ /* reserved 6 ~ 16 */ #endif /* _ASM_NDS32_NDS32_H_ */