/usr/src/linux-headers-5.15.0-190/arch/openrisc/include/asm
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bitops/-0755rm
asm-offsets.h350644editdlrm
atomic.h36090644editdlrm
barrier.h2410644editdlrm
bitops.h13260644editdlrm
cache.h6810644editdlrm
cacheflush.h22040644editdlrm
cmpxchg.h40560644editdlrm
cpuinfo.h7630644editdlrm
delay.h4630644editdlrm
elf.h18600644editdlrm
fixmap.h25960644editdlrm
futex.h22930644editdlrm
io.h8330644editdlrm
irq.h5610644editdlrm
irqflags.h6590644editdlrm
Kbuild2380644editdlrm
linkage.h5570644editdlrm
mmu.h5210644editdlrm
mmu_context.h11080644editdlrm
page.h22880644editdlrm
pgalloc.h18310644editdlrm
pgtable.h127490644editdlrm
processor.h23390644editdlrm
ptrace.h32010644editdlrm
serial.h9280644editdlrm
setup.h2930644editdlrm
smp.h8220644editdlrm
spinlock.h7780644editdlrm
spinlock_types.h1880644editdlrm
spr.h9910644editdlrm
spr_defs.h232520644editdlrm
string.h3240644editdlrm
syscall.h16580644editdlrm
syscalls.h9690644editdlrm
thread_info.h37870644editdlrm
time.h6270644editdlrm
timex.h7070644editdlrm
tlb.h6510644editdlrm
tlbflush.h18440644editdlrm
uaccess.h79850644editdlrm
unwinder.h5570644editdlrm
vmalloc.h1020644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/arch/openrisc/include/asm/cacheflush.h (2204B)
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * OpenRISC Linux * * Linux architectural port borrowing liberally from similar works of * others. All original copyrights apply as per the original source * declaration. * * OpenRISC implementation: * Copyright (C) Jan Henrik Weinstock * et al. */ #ifndef __ASM_CACHEFLUSH_H #define __ASM_CACHEFLUSH_H #include /* * Helper function for flushing or invalidating entire pages from data * and instruction caches. SMP needs a little extra work, since we need * to flush the pages on all cpus. */ extern void local_dcache_page_flush(struct page *page); extern void local_icache_page_inv(struct page *page); /* * Data cache flushing always happen on the local cpu. Instruction cache * invalidations need to be broadcasted to all other cpu in the system in * case of SMP configurations. */ #ifndef CONFIG_SMP #define dcache_page_flush(page) local_dcache_page_flush(page) #define icache_page_inv(page) local_icache_page_inv(page) #else /* CONFIG_SMP */ #define dcache_page_flush(page) local_dcache_page_flush(page) #define icache_page_inv(page) smp_icache_page_inv(page) extern void smp_icache_page_inv(struct page *page); #endif /* CONFIG_SMP */ /* * Synchronizes caches. Whenever a cpu writes executable code to memory, this * should be called to make sure the processor sees the newly written code. */ static inline void sync_icache_dcache(struct page *page) { if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH)) dcache_page_flush(page); icache_page_inv(page); } /* * Pages with this bit set need not be flushed/invalidated, since * they have not changed since last flush. New pages start with * PG_arch_1 not set and are therefore dirty by default. */ #define PG_dc_clean PG_arch_1 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 static inline void flush_dcache_page(struct page *page) { clear_bit(PG_dc_clean, &page->flags); } #define flush_icache_user_page(vma, page, addr, len) \ do { \ if (vma->vm_flags & VM_EXEC) \ sync_icache_dcache(page); \ } while (0) #include #endif /* __ASM_CACHEFLUSH_H */