/usr/src/linux-headers-5.15.0-190/arch/xtensa/include/asm/
/usr/src/linux-headers-5.15.0-190/arch/xtensa/include/asm
NameSizeModeActions
asm-offsets.h350644editdlrm
asm-uaccess.h41800644editdlrm
asmmacro.h47630644editdlrm
atomic.h73010644editdlrm
barrier.h5940644editdlrm
bitops.h53980644editdlrm
bootparam.h14020644editdlrm
cache.h11140644editdlrm
cacheasm.h38560644editdlrm
cacheflush.h59680644editdlrm
checksum.h58930644editdlrm
cmpxchg.h56840644editdlrm
coprocessor.h46230644editdlrm
core.h8300644editdlrm
current.h6790644editdlrm
delay.h16680644editdlrm
dma.h18300644editdlrm
elf.h51150644editdlrm
fixmap.h11060644editdlrm
flat.h4400644editdlrm
ftrace.h9790644editdlrm
futex.h38890644editdlrm
highmem.h21670644editdlrm
hw_breakpoint.h15970644editdlrm
initialize_mmu.h51960644editdlrm
io.h19590644editdlrm
irq.h11270644editdlrm
irqflags.h20690644editdlrm
jump_label.h16550644editdlrm
kasan.h8590644editdlrm
Kbuild2300644editdlrm
kmem_layout.h27900644editdlrm
linkage.h1540644editdlrm
mmu.h4620644editdlrm
mmu_context.h36240644editdlrm
mxregs.h13300644editdlrm
nommu_context.h1560644editdlrm
page.h57930644editdlrm
pci-bridge.h21700644editdlrm
pci.h13020644editdlrm
perf_event.h1080644editdlrm
pgalloc.h14050644editdlrm
pgtable.h144700644editdlrm
platform.h15280644editdlrm
processor.h77050644editdlrm
ptrace.h33210644editdlrm
regs.h40170644editdlrm
seccomp.h2870644editdlrm
serial.h4430644editdlrm
shmparam.h5610644editdlrm
signal.h5020644editdlrm
smp.h9670644editdlrm
spinlock.h4720644editdlrm
spinlock_types.h3170644editdlrm
stackprotector.h11400644editdlrm
stacktrace.h11580644editdlrm
string.h33850644editdlrm
switch_to.h6010644editdlrm
syscall.h21400644editdlrm
sysmem.h4260644editdlrm
thread_info.h39650644editdlrm
timex.h14400644editdlrm
tlb.h4750644editdlrm
tlbflush.h56200644editdlrm
traps.h27790644editdlrm
uaccess.h93750644editdlrm
ucontext.h5400644editdlrm
unistd.h3700644editdlrm
vectors.h32760644editdlrm
vermagic.h4330644editdlrm
vmalloc.h960644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/arch/xtensa/include/asm/mxregs.h (1330B)
/* * Xtensa MX interrupt distributor * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2008 - 2013 Tensilica Inc. */ #ifndef _XTENSA_MXREGS_H #define _XTENSA_MXREGS_H /* * RER/WER at, as Read/write external register * at: value * as: address * * Address Value * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p * 0180 0...0m..m Clear enable specified by mask (m) * 0184 0...0m..m Set enable specified by mask (m) * 0190 0...0x..x 8-bit IPI partition register * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU * V (10-bit) Release/Version * P ( 4-bit) Number of cores - 1 * U (18-bit) ID * 01a0 i.......i 32-bit ConfigID * 0200 0...0m..m RunStall core 'n' * 0220 c Cache coherency enabled */ #define MIROUT(irq) (0x000 + (irq)) #define MIPICAUSE(cpu) (0x100 + (cpu)) #define MIPISET(cause) (0x140 + (cause)) #define MIENG 0x180 #define MIENGSET 0x184 #define MIASG 0x188 /* Read Global Assert Register */ #define MIASGSET 0x18c /* Set Global Addert Regiter */ #define MIPIPART 0x190 #define SYSCFGID 0x1a0 #define MPSCORE 0x200 #define CCON 0x220 #endif /* _XTENSA_MXREGS_H */