/usr/src/linux-headers-5.15.0-190/include/linux/irqchip
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arm-gic-common.h6260644editdlrm
arm-gic-v3.h243780644editdlrm
arm-gic-v4.h36380644editdlrm
arm-gic.h55270644editdlrm
arm-vgic-info.h10010644editdlrm
arm-vic.h3530644editdlrm
chained_irq.h9310644editdlrm
irq-bcm2836.h19350644editdlrm
irq-davinci-aintc.h6740644editdlrm
irq-davinci-cp-intc.h6160644editdlrm
irq-ixp4xx.h2760644editdlrm
irq-madera.h37450644editdlrm
irq-omap-intc.h5670644editdlrm
irq-partition-percpu.h13550644editdlrm
irq-sa11x0.h3560644editdlrm
mmp.h1550644editdlrm
mxs.h2210644editdlrm
versatile-fpga.h3530644editdlrm
xtensa-mx.h4670644editdlrm
xtensa-pic.h5320644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/include/linux/irqchip/chained_irq.h (931B)
/* SPDX-License-Identifier: GPL-2.0-only */ /* * Chained IRQ handlers support. * * Copyright (C) 2011 ARM Ltd. */ #ifndef __IRQCHIP_CHAINED_IRQ_H #define __IRQCHIP_CHAINED_IRQ_H #include /* * Entry/exit functions for chained handlers where the primary IRQ chip * may implement either fasteoi or level-trigger flow control. */ static inline void chained_irq_enter(struct irq_chip *chip, struct irq_desc *desc) { /* FastEOI controllers require no action on entry. */ if (chip->irq_eoi) return; if (chip->irq_mask_ack) { chip->irq_mask_ack(&desc->irq_data); } else { chip->irq_mask(&desc->irq_data); if (chip->irq_ack) chip->irq_ack(&desc->irq_data); } } static inline void chained_irq_exit(struct irq_chip *chip, struct irq_desc *desc) { if (chip->irq_eoi) chip->irq_eoi(&desc->irq_data); else chip->irq_unmask(&desc->irq_data); } #endif /* __IRQCHIP_CHAINED_IRQ_H */