/usr/src/linux-headers-5.15.0-190/include/video
NameSizeModeActions
atmel_lcdc.h62980644editdlrm
aty128.h135930644editdlrm
broadsheetfb.h21690644editdlrm
cirrus.h58010644editdlrm
cvisionppc.h15770644editdlrm
da8xx-fb.h20030644editdlrm
display_timing.h31880644editdlrm
edid.h2280644editdlrm
gbe.h106940644editdlrm
hecubafb.h15400644editdlrm
ili9320.h57940644editdlrm
imx-ipu-image-convert.h66850644editdlrm
imx-ipu-v3.h167770644editdlrm
kyro.h24190644editdlrm
mach64.h480590644editdlrm
maxinefb.h12680644editdlrm
metronomefb.h15200644editdlrm
mipi_display.h50740644editdlrm
mmp_disp.h71880644editdlrm
neomagic.h50140644editdlrm
newport.h191260644editdlrm
of_display_timing.h8140644editdlrm
of_videomode.h3670644editdlrm
omap-panel-data.h16970644editdlrm
omapfb_dss.h244790644editdlrm
omapvrfb.h18330644editdlrm
permedia2.h91750644editdlrm
platform_lcd.h4400644editdlrm
pm3fb.h463990644editdlrm
pmag-ba-fb.h10480644editdlrm
pmagb-b-fb.h24000644editdlrm
pxa168fb.h25930644editdlrm
radeon.h1118360644editdlrm
s1d13xxxfb.h101880644editdlrm
sa1100fb.h12940644editdlrm
samsung_fimd.h174250644editdlrm
sh_mobile_lcdc.h61350644editdlrm
sisfb.h6060644editdlrm
sstfb.h113330644editdlrm
tdfx.h54450644editdlrm
tgafb.h71060644editdlrm
trident.h33120644editdlrm
udlfb.h29980644editdlrm
uvesafb.h29200644editdlrm
vga.h140530644editdlrm
videomode.h13790644editdlrm
w100fb.h36560644editdlrm
Edit: /usr/src/linux-headers-5.15.0-190/include/video/pxa168fb.h (2593B)
/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2009 Marvell International Ltd. */ #ifndef __ASM_MACH_PXA168FB_H #define __ASM_MACH_PXA168FB_H #include #include /* Dumb interface */ #define PIN_MODE_DUMB_24 0 #define PIN_MODE_DUMB_18_SPI 1 #define PIN_MODE_DUMB_18_GPIO 2 #define PIN_MODE_DUMB_16_SPI 3 #define PIN_MODE_DUMB_16_GPIO 4 #define PIN_MODE_DUMB_12_SPI_GPIO 5 #define PIN_MODE_SMART_18_SPI 6 #define PIN_MODE_SMART_16_SPI 7 #define PIN_MODE_SMART_8_SPI_GPIO 8 /* Dumb interface pin allocation */ #define DUMB_MODE_RGB565 0 #define DUMB_MODE_RGB565_UPPER 1 #define DUMB_MODE_RGB666 2 #define DUMB_MODE_RGB666_UPPER 3 #define DUMB_MODE_RGB444 4 #define DUMB_MODE_RGB444_UPPER 5 #define DUMB_MODE_RGB888 6 /* default fb buffer size WVGA-32bits */ #define DEFAULT_FB_SIZE (800 * 480 * 4) /* * Buffer pixel format * bit0 is for rb swap. * bit12 is for Y UorV swap */ #define PIX_FMT_RGB565 0 #define PIX_FMT_BGR565 1 #define PIX_FMT_RGB1555 2 #define PIX_FMT_BGR1555 3 #define PIX_FMT_RGB888PACK 4 #define PIX_FMT_BGR888PACK 5 #define PIX_FMT_RGB888UNPACK 6 #define PIX_FMT_BGR888UNPACK 7 #define PIX_FMT_RGBA888 8 #define PIX_FMT_BGRA888 9 #define PIX_FMT_YUV422PACK 10 #define PIX_FMT_YVU422PACK 11 #define PIX_FMT_YUV422PLANAR 12 #define PIX_FMT_YVU422PLANAR 13 #define PIX_FMT_YUV420PLANAR 14 #define PIX_FMT_YVU420PLANAR 15 #define PIX_FMT_PSEUDOCOLOR 20 #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) /* * PXA LCD controller private state. */ struct pxa168fb_info { struct device *dev; struct clk *clk; struct fb_info *info; void __iomem *reg_base; dma_addr_t fb_start_dma; u32 pseudo_palette[16]; int pix_fmt; unsigned is_blanked:1; unsigned panel_rbswap:1; unsigned active:1; }; /* * PXA fb machine information */ struct pxa168fb_mach_info { char id[16]; int num_modes; struct fb_videomode *modes; /* * Pix_fmt */ unsigned pix_fmt; /* * I/O pin allocation. */ unsigned io_pin_allocation_mode:4; /* * Dumb panel -- assignment of R/G/B component info to the 24 * available external data lanes. */ unsigned dumb_mode:4; unsigned panel_rgb_reverse_lanes:1; /* * Dumb panel -- GPIO output data. */ unsigned gpio_output_mask:8; unsigned gpio_output_data:8; /* * Dumb panel -- configurable output signal polarity. */ unsigned invert_composite_blank:1; unsigned invert_pix_val_ena:1; unsigned invert_pixclock:1; unsigned panel_rbswap:1; unsigned active:1; unsigned enable_lcd:1; }; #endif /* __ASM_MACH_PXA168FB_H */