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/usr/include/boost/atomic/detail

Name	Size	Mode	Actions
type_traits/	-	0755	rm
addressof.hpp	1973	0644	edit dl rm
aligned_variable.hpp	1853	0644	edit dl rm
atomic_flag_impl.hpp	4525	0644	edit dl rm
atomic_impl.hpp	56095	0644	edit dl rm
atomic_ref_impl.hpp	54073	0644	edit dl rm
bitwise_cast.hpp	2691	0644	edit dl rm
bitwise_fp_cast.hpp	2509	0644	edit dl rm
capabilities.hpp	7520	0644	edit dl rm
caps_arch_gcc_aarch32.hpp	1617	0644	edit dl rm
caps_arch_gcc_aarch64.hpp	2238	0644	edit dl rm
caps_arch_gcc_alpha.hpp	940	0644	edit dl rm
caps_arch_gcc_arm.hpp	3573	0644	edit dl rm
caps_arch_gcc_ppc.hpp	1581	0644	edit dl rm
caps_arch_gcc_sparc.hpp	940	0644	edit dl rm
caps_arch_gcc_x86.hpp	2013	0644	edit dl rm
caps_arch_msvc_arm.hpp	943	0644	edit dl rm
caps_arch_msvc_x86.hpp	1698	0644	edit dl rm
caps_gcc_atomic.hpp	7438	0644	edit dl rm
caps_gcc_sync.hpp	1715	0644	edit dl rm
caps_linux_arm.hpp	963	0644	edit dl rm
caps_windows.hpp	880	0644	edit dl rm
cas_based_exchange.hpp	1348	0644	edit dl rm
classify.hpp	2133	0644	edit dl rm
config.hpp	7945	0644	edit dl rm
core_arch_operations.hpp	1481	0644	edit dl rm
core_arch_operations_fwd.hpp	972	0644	edit dl rm
core_arch_ops_gcc_aarch32.hpp	41910	0644	edit dl rm
core_arch_ops_gcc_aarch64.hpp	69364	0644	edit dl rm
core_arch_ops_gcc_alpha.hpp	27813	0644	edit dl rm
core_arch_ops_gcc_arm.hpp	64434	0644	edit dl rm
core_arch_ops_gcc_ppc.hpp	39185	0644	edit dl rm
core_arch_ops_gcc_sparc.hpp	7480	0644	edit dl rm
core_arch_ops_gcc_x86.hpp	39479	0644	edit dl rm
core_arch_ops_msvc_arm.hpp	34246	0644	edit dl rm
core_arch_ops_msvc_x86.hpp	31645	0644	edit dl rm
core_operations.hpp	1322	0644	edit dl rm
core_operations_emulated.hpp	8138	0644	edit dl rm
core_operations_emulated_fwd.hpp	1024	0644	edit dl rm
core_operations_fwd.hpp	942	0644	edit dl rm
core_ops_cas_based.hpp	3281	0644	edit dl rm
core_ops_gcc_atomic.hpp	12238	0644	edit dl rm
core_ops_gcc_sync.hpp	10690	0644	edit dl rm
core_ops_linux_arm.hpp	6364	0644	edit dl rm
core_ops_windows.hpp	7766	0644	edit dl rm
extending_cas_based_arithmetic.hpp	2441	0644	edit dl rm
extra_fp_operations.hpp	867	0644	edit dl rm
extra_fp_operations_fwd.hpp	1065	0644	edit dl rm
extra_fp_ops_emulated.hpp	4864	0644	edit dl rm
extra_fp_ops_generic.hpp	7222	0644	edit dl rm
extra_operations.hpp	825	0644	edit dl rm
extra_operations_fwd.hpp	1034	0644	edit dl rm
extra_ops_emulated.hpp	11876	0644	edit dl rm
extra_ops_gcc_aarch32.hpp	37869	0644	edit dl rm
extra_ops_gcc_aarch64.hpp	47028	0644	edit dl rm
extra_ops_gcc_arm.hpp	52836	0644	edit dl rm
extra_ops_gcc_ppc.hpp	28665	0644	edit dl rm
extra_ops_gcc_x86.hpp	58227	0644	edit dl rm
extra_ops_generic.hpp	17217	0644	edit dl rm
extra_ops_msvc_arm.hpp	3765	0644	edit dl rm
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fence_arch_operations.hpp	1077	0644	edit dl rm
fence_arch_ops_gcc_aarch32.hpp	1701	0644	edit dl rm
fence_arch_ops_gcc_aarch64.hpp	1624	0644	edit dl rm
fence_arch_ops_gcc_alpha.hpp	1411	0644	edit dl rm
fence_arch_ops_gcc_arm.hpp	2769	0644	edit dl rm
fence_arch_ops_gcc_ppc.hpp	1773	0644	edit dl rm
fence_arch_ops_gcc_sparc.hpp	2002	0644	edit dl rm
fence_arch_ops_gcc_x86.hpp	2557	0644	edit dl rm
fence_arch_ops_msvc_arm.hpp	1787	0644	edit dl rm
fence_arch_ops_msvc_x86.hpp	1998	0644	edit dl rm
fence_operations.hpp	1007	0644	edit dl rm
fence_operations_emulated.hpp	1294	0644	edit dl rm
fence_ops_gcc_atomic.hpp	2399	0644	edit dl rm
fence_ops_gcc_sync.hpp	1367	0644	edit dl rm
fence_ops_linux_arm.hpp	1792	0644	edit dl rm
fence_ops_windows.hpp	1848	0644	edit dl rm
float_sizes.hpp	7570	0644	edit dl rm
footer.hpp	505	0644	edit dl rm
fp_operations.hpp	807	0644	edit dl rm
fp_operations_fwd.hpp	1001	0644	edit dl rm
fp_ops_emulated.hpp	2714	0644	edit dl rm
fp_ops_generic.hpp	2919	0644	edit dl rm
futex.hpp	5388	0644	edit dl rm
gcc_arm_asm_common.hpp	4031	0644	edit dl rm
gcc_atomic_memory_order_utils.hpp	2804	0644	edit dl rm
header.hpp	2624	0644	edit dl rm
integral_conversions.hpp	4306	0644	edit dl rm
interlocked.hpp	34503	0644	edit dl rm
intptr.hpp	992	0644	edit dl rm
int_sizes.hpp	4987	0644	edit dl rm
link.hpp	1534	0644	edit dl rm
lock_pool.hpp	4689	0644	edit dl rm
memory_order_utils.hpp	1576	0644	edit dl rm
once_flag.hpp	1136	0644	edit dl rm
ops_gcc_aarch32_common.hpp	1577	0644	edit dl rm
ops_gcc_aarch64_common.hpp	1467	0644	edit dl rm
ops_gcc_arm_common.hpp	1963	0644	edit dl rm
ops_gcc_ppc_common.hpp	2762	0644	edit dl rm
ops_msvc_common.hpp	1318	0644	edit dl rm
pause.hpp	1494	0644	edit dl rm
platform.hpp	7210	0644	edit dl rm
storage_traits.hpp	5448	0644	edit dl rm
string_ops.hpp	1719	0644	edit dl rm
wait_capabilities.hpp	16861	0644	edit dl rm
wait_caps_dragonfly_umtx.hpp	1055	0644	edit dl rm
wait_caps_freebsd_umtx.hpp	1539	0644	edit dl rm
wait_caps_futex.hpp	1027	0644	edit dl rm
wait_caps_windows.hpp	2340	0644	edit dl rm
wait_operations.hpp	828	0644	edit dl rm
wait_operations_fwd.hpp	1071	0644	edit dl rm
wait_ops_dragonfly_umtx.hpp	2354	0644	edit dl rm
wait_ops_emulated.hpp	3296	0644	edit dl rm
wait_ops_freebsd_umtx.hpp	3974	0644	edit dl rm
wait_ops_futex.hpp	3416	0644	edit dl rm
wait_ops_generic.hpp	4263	0644	edit dl rm
wait_ops_windows.hpp	4848	0644	edit dl rm

Edit: /usr/include/boost/atomic/detail/gcc_arm_asm_common.hpp (4031B)

/*
 * Distributed under the Boost Software License, Version 1.0.
 * (See accompanying file LICENSE_1_0.txt or copy at
 * http://www.boost.org/LICENSE_1_0.txt)
 *
 * Copyright (c) 2009 Helge Bahmann
 * Copyright (c) 2013 Tim Blechmann
 * Copyright (c) 2014, 2020 Andrey Semashev
 */
/*!
 * \file   atomic/detail/gcc_arm_asm_common.hpp
 *
 * This header contains basic utilities for gcc asm-based ARM backend.
 */

#ifndef BOOST_ATOMIC_DETAIL_GCC_ARM_ASM_COMMON_HPP_INCLUDED_
#define BOOST_ATOMIC_DETAIL_GCC_ARM_ASM_COMMON_HPP_INCLUDED_

#include <boost/atomic/detail/config.hpp>
#include <boost/atomic/detail/capabilities.hpp>

// A memory barrier is effected using a "co-processor 15" instruction,
// though a separate assembler mnemonic is available for it in v7.
//
// "Thumb 1" is a subset of the ARM instruction set that uses a 16-bit encoding.  It
// doesn't include all instructions and in particular it doesn't include the co-processor
// instruction used for the memory barrier or the load-locked/store-conditional
// instructions.  So, if we're compiling in "Thumb 1" mode, we need to wrap all of our
// asm blocks with code to temporarily change to ARM mode.
//
// You can only change between ARM and Thumb modes when branching using the bx instruction.
// bx takes an address specified in a register.  The least significant bit of the address
// indicates the mode, so 1 is added to indicate that the destination code is Thumb.
// A temporary register is needed for the address and is passed as an argument to these
// macros.  It must be one of the "low" registers accessible to Thumb code, specified
// using the "l" attribute in the asm statement.
//
// Architecture v7 introduces "Thumb 2", which does include (almost?) all of the ARM
// instruction set.  (Actually, there was an extension of v6 called v6T2 which supported
// "Thumb 2" mode, but its architecture manual is no longer available, referring to v7.)
// So in v7 we don't need to change to ARM mode; we can write "universal
// assembler" which will assemble to Thumb 2 or ARM code as appropriate.  The only thing
// we need to do to make this "universal" assembler mode work is to insert "IT" instructions
// to annotate the conditional instructions.  These are ignored in other modes (e.g. v6),
// so they can always be present.

// A note about memory_order_consume. Technically, this architecture allows to avoid
// unnecessary memory barrier after consume load since it supports data dependency ordering.
// However, some compiler optimizations may break a seemingly valid code relying on data
// dependency tracking by injecting bogus branches to aid out of order execution.
// This may happen not only in Boost.Atomic code but also in user's code, which we have no
// control of. See this thread: http://lists.boost.org/Archives/boost/2014/06/213890.php.
// For this reason we promote memory_order_consume to memory_order_acquire.

#if defined(__thumb__) && !defined(__thumb2__)
#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 8f\n\t" "bx " #TMPREG "\n\t" ".arm\n\t" ".align 4\n\t" "8:\n\t"
#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)   "adr " #TMPREG ", 9f + 1\n\t" "bx " #TMPREG "\n\t" ".thumb\n\t" ".align 2\n\t" "9:\n\t"
#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
#else
// Indicate that start/end macros are empty and the tmpreg is not needed
#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_UNUSED
#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG)
#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)
#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
#endif

#if defined(BOOST_ATOMIC_DETAIL_ARM_LITTLE_ENDIAN)
#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_LO(arg) "%" BOOST_STRINGIZE(arg)
#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_HI(arg) "%H" BOOST_STRINGIZE(arg)
#else
#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_LO(arg) "%H" BOOST_STRINGIZE(arg)
#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_HI(arg) "%" BOOST_STRINGIZE(arg)
#endif

#endif // BOOST_ATOMIC_DETAIL_GCC_ARM_ASM_COMMON_HPP_INCLUDED_

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