FM / asm

/usr/src/linux-headers-5.15.0-181/arch/alpha/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/alpha/include/asm

Name	Size	Mode	Actions
a.out.h	574	0644	edit dl rm
agp.h	490	0644	edit dl rm
agp_backend.h	948	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	505	0644	edit dl rm
atomic.h	8749	0644	edit dl rm
barrier.h	507	0644	edit dl rm
bitops.h	9039	0644	edit dl rm
bug.h	571	0644	edit dl rm
cache.h	507	0644	edit dl rm
cacheflush.h	2039	0644	edit dl rm
checksum.h	2012	0644	edit dl rm
cmpxchg.h	1928	0644	edit dl rm
compiler.h	158	0644	edit dl rm
console.h	1084	0644	edit dl rm
core_apecs.h	17338	0644	edit dl rm
core_cia.h	15817	0644	edit dl rm
core_irongate.h	6793	0644	edit dl rm
core_lca.h	11650	0644	edit dl rm
core_marvel.h	9382	0644	edit dl rm
core_mcpcia.h	11747	0644	edit dl rm
core_polaris.h	2987	0644	edit dl rm
core_t2.h	19595	0644	edit dl rm
core_titan.h	11471	0644	edit dl rm
core_tsunami.h	8485	0644	edit dl rm
core_wildfire.h	8655	0644	edit dl rm
delay.h	264	0644	edit dl rm
device.h	129	0644	edit dl rm
div64.h	31	0644	edit dl rm
dma-mapping.h	342	0644	edit dl rm
dma.h	12664	0644	edit dl rm
elf.h	5765	0644	edit dl rm
emergency-restart.h	149	0644	edit dl rm
err_common.h	3316	0644	edit dl rm
err_ev6.h	116	0644	edit dl rm
err_ev7.h	4472	0644	edit dl rm
extable.h	1459	0644	edit dl rm
floppy.h	3171	0644	edit dl rm
fpu.h	1820	0644	edit dl rm
ftrace.h	12	0644	edit dl rm
futex.h	2017	0644	edit dl rm
gct.h	1042	0644	edit dl rm
hardirq.h	223	0644	edit dl rm
hwrpb.h	7066	0644	edit dl rm
hw_irq.h	302	0644	edit dl rm
io.h	14873	0644	edit dl rm
io_trivial.h	3206	0644	edit dl rm
irq.h	2363	0644	edit dl rm
irqflags.h	1194	0644	edit dl rm
irq_regs.h	34	0644	edit dl rm
jensen.h	8603	0644	edit dl rm
Kbuild	141	0644	edit dl rm
kdebug.h	32	0644	edit dl rm
linkage.h	256	0644	edit dl rm
local.h	2654	0644	edit dl rm
machvec.h	3621	0644	edit dl rm
mc146818rtc.h	680	0644	edit dl rm
mce.h	4135	0644	edit dl rm
mmu.h	203	0644	edit dl rm
mmu_context.h	7241	0644	edit dl rm
module.h	329	0644	edit dl rm
page.h	2397	0644	edit dl rm
pal.h	5127	0644	edit dl rm
param.h	284	0644	edit dl rm
parport.h	536	0644	edit dl rm
pci.h	2733	0644	edit dl rm
percpu.h	527	0644	edit dl rm
perf_event.h	105	0644	edit dl rm
pgalloc.h	761	0644	edit dl rm
pgtable.h	12577	0644	edit dl rm
processor.h	1677	0644	edit dl rm
ptrace.h	754	0644	edit dl rm
rwonce.h	812	0644	edit dl rm
serial.h	1034	0644	edit dl rm
setup.h	1465	0644	edit dl rm
sfp-machine.h	2929	0644	edit dl rm
shmparam.h	191	0644	edit dl rm
signal.h	627	0644	edit dl rm
smp.h	1377	0644	edit dl rm
socket.h	310	0644	edit dl rm
sparsemem.h	410	0644	edit dl rm
special_insns.h	925	0644	edit dl rm
spinlock.h	2915	0644	edit dl rm
spinlock_types.h	413	0644	edit dl rm
string.h	2481	0644	edit dl rm
switch_to.h	406	0644	edit dl rm
syscall.h	379	0644	edit dl rm
termios.h	3054	0644	edit dl rm
thread_info.h	3749	0644	edit dl rm
timex.h	827	0644	edit dl rm
tlb.h	257	0644	edit dl rm
tlbflush.h	3424	0644	edit dl rm
topology.h	271	0644	edit dl rm
types.h	143	0644	edit dl rm
uaccess.h	9767	0644	edit dl rm
ucontext.h	348	0644	edit dl rm
unistd.h	561	0644	edit dl rm
user.h	2192	0644	edit dl rm
vga.h	2050	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm
word-at-a-time.h	1376	0644	edit dl rm
wrperfmon.h	2623	0644	edit dl rm
xchg.h	5287	0644	edit dl rm
xor.h	21833	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/alpha/include/asm/core_irongate.h (6793B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ALPHA_IRONGATE__H__
#define __ALPHA_IRONGATE__H__

#include <linux/types.h>
#include <asm/compiler.h>

/*
 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
 * which provides memory controller and PCI access for NAUTILUS-based
 * EV6 (21264) systems.
 *
 * This file is based on:
 *
 * IronGate management library, (c) 1999 Alpha Processor, Inc.
 * Copyright (C) 1999 Alpha Processor, Inc.,
 *	(David Daniel, Stig Telfer, Soohoon Lee)
 */

/*
 * The 21264 supports, and internally recognizes, a 44-bit physical
 * address space that is divided equally between memory address space
 * and I/O address space. Memory address space resides in the lower
 * half of the physical address space (PA[43]=0) and I/O address space
 * resides in the upper half of the physical address space (PA[43]=1).
 */

/*
 * Irongate CSR map.  Some of the CSRs are 8 or 16 bits, but all access
 * through the routines given is 32-bit.
 *
 * The first 0x40 bytes are standard as per the PCI spec.
 */

typedef volatile __u32	igcsr32;

typedef struct {
	igcsr32 dev_vendor;		/* 0x00 - device ID, vendor ID */
	igcsr32 stat_cmd;		/* 0x04 - status, command */
	igcsr32 class;			/* 0x08 - class code, rev ID */
	igcsr32 latency;		/* 0x0C - header type, PCI latency */
	igcsr32 bar0;			/* 0x10 - BAR0 - AGP */
	igcsr32 bar1;			/* 0x14 - BAR1 - GART */
	igcsr32 bar2;			/* 0x18 - Power Management reg block */

igcsr32 rsrvd0[6];		/* 0x1C-0x33 reserved */

igcsr32 capptr;			/* 0x34 - Capabilities pointer */

igcsr32 rsrvd1[2];		/* 0x38-0x3F reserved */

igcsr32 bacsr10;		/* 0x40 - base address chip selects */
	igcsr32 bacsr32;		/* 0x44 - base address chip selects */
	igcsr32 bacsr54_eccms761;	/* 0x48 - 751: base addr. chip selects
						  761: ECC, mode/status */

igcsr32 rsrvd2[1];		/* 0x4C-0x4F reserved */

igcsr32 drammap;		/* 0x50 - address mapping control */
	igcsr32 dramtm;			/* 0x54 - timing, driver strength */
	igcsr32 dramms;			/* 0x58 - DRAM mode/status */

igcsr32 rsrvd3[1];		/* 0x5C-0x5F reserved */

igcsr32 biu0;			/* 0x60 - bus interface unit */
	igcsr32 biusip;			/* 0x64 - Serial initialisation pkt */

igcsr32 rsrvd4[2];		/* 0x68-0x6F reserved */

igcsr32 mro;			/* 0x70 - memory request optimiser */

igcsr32 rsrvd5[3];		/* 0x74-0x7F reserved */

igcsr32 whami;			/* 0x80 - who am I */
	igcsr32 pciarb;			/* 0x84 - PCI arbitration control */
	igcsr32 pcicfg;			/* 0x88 - PCI config status */

igcsr32 rsrvd6[4];		/* 0x8C-0x9B reserved */

igcsr32 pci_mem;		/* 0x9C - PCI top of memory,
						  761 only */

/* AGP (bus 1) control registers */
	igcsr32 agpcap;			/* 0xA0 - AGP Capability Identifier */
	igcsr32 agpstat;		/* 0xA4 - AGP status register */
	igcsr32 agpcmd;			/* 0xA8 - AGP control register */
	igcsr32 agpva;			/* 0xAC - AGP Virtual Address Space */
	igcsr32 agpmode;		/* 0xB0 - AGP/GART mode control */
} Irongate0;

typedef struct {

igcsr32 dev_vendor;		/* 0x00 - Device and Vendor IDs */
	igcsr32 stat_cmd;		/* 0x04 - Status and Command regs */
	igcsr32 class;			/* 0x08 - subclass, baseclass etc */
	igcsr32 htype;			/* 0x0C - header type (at 0x0E) */
	igcsr32 rsrvd0[2];		/* 0x10-0x17 reserved */
	igcsr32 busnos;			/* 0x18 - Primary, secondary bus nos */
	igcsr32 io_baselim_regs;	/* 0x1C - IO base, IO lim, AGP status */
	igcsr32	mem_baselim;		/* 0x20 - memory base, memory lim */
	igcsr32 pfmem_baselim;		/* 0x24 - prefetchable base, lim */
	igcsr32 rsrvd1[2];		/* 0x28-0x2F reserved */
	igcsr32 io_baselim;		/* 0x30 - IO base, IO limit */
	igcsr32 rsrvd2[2];		/* 0x34-0x3B - reserved */
	igcsr32 interrupt;		/* 0x3C - interrupt, PCI bridge ctrl */

} Irongate1;

extern igcsr32 *IronECC;

/*
 * Memory spaces:
 */

/* Irongate is consistent with a subset of the Tsunami memory map */
#ifdef USE_48_BIT_KSEG
#define IRONGATE_BIAS 0x80000000000UL
#else
#define IRONGATE_BIAS 0x10000000000UL
#endif

/*
 * PCI Configuration space accesses are formed like so:
 *
 * 0x1FE << 24 |  : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
 *                : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
 *                  ---bus numer---   -device-- -fun-   ---register----
 */

#define IGCSR(dev,fun,reg)	( IRONGATE_CONF | \
				((dev)<<11) | \
				((fun)<<8) | \
				(reg) )

#define IRONGATE0		((Irongate0 *) IGCSR(0, 0, 0))
#define IRONGATE1		((Irongate1 *) IGCSR(1, 0, 0))

/*
 * Data structure for handling IRONGATE machine checks:
 * This is the standard OSF logout frame
 */

#define SCB_Q_SYSERR	0x620			/* OSF definitions */
#define SCB_Q_PROCERR	0x630
#define SCB_Q_SYSMCHK	0x660
#define SCB_Q_PROCMCHK	0x670

struct el_IRONGATE_sysdata_mcheck {
	__u32 FrameSize;                 /* Bytes, including this field */
	__u32 FrameFlags;                /* <31> = Retry, <30> = Second Error */
	__u32 CpuOffset;                 /* Offset to CPU-specific into */
	__u32 SystemOffset;              /* Offset to system-specific info */
	__u32 MCHK_Code;
	__u32 MCHK_Frame_Rev;
	__u64 I_STAT;
	__u64 DC_STAT;
	__u64 C_ADDR;
	__u64 DC1_SYNDROME;
	__u64 DC0_SYNDROME;
	__u64 C_STAT;
	__u64 C_STS;
	__u64 RESERVED0;
	__u64 EXC_ADDR;
	__u64 IER_CM;
	__u64 ISUM;
	__u64 MM_STAT;
	__u64 PAL_BASE;
	__u64 I_CTL;
	__u64 PCTX;
};

#ifdef __KERNEL__

#ifndef __EXTERN_INLINE
#define __EXTERN_INLINE extern inline
#define __IO_EXTERN_INLINE
#endif

/*
 * I/O functions:
 *
 * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
 * K7 can only use linear accesses to get at PCI memory and I/O spaces.
 */

/*
 * Memory functions.  All accesses are done through linear space.
 */

__EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
{
	return (void __iomem *)(addr + IRONGATE_IO);
}

extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
extern void irongate_iounmap(volatile void __iomem *addr);

__EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
{
	return addr >= IRONGATE_MEM;
}

__EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr;
	return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
}

#undef __IO_PREFIX
#define __IO_PREFIX			irongate
#define irongate_trivial_rw_bw		1
#define irongate_trivial_rw_lq		1
#define irongate_trivial_io_bw		1
#define irongate_trivial_io_lq		1
#define irongate_trivial_iounmap	0
#include <asm/io_trivial.h>

#ifdef __IO_EXTERN_INLINE
#undef __EXTERN_INLINE
#undef __IO_EXTERN_INLINE
#endif

#endif /* __KERNEL__ */

#endif /* __ALPHA_IRONGATE__H__ */

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