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/usr/src/linux-headers-5.15.0-181/arch/arc/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/arc/include/asm

Name	Size	Mode	Actions
arcregs.h	9477	0644	edit dl rm
asm-offsets.h	165	0644	edit dl rm
asserts.h	958	0644	edit dl rm
atomic-llsc.h	2864	0644	edit dl rm
atomic-spinlock.h	2569	0644	edit dl rm
atomic.h	1153	0644	edit dl rm
atomic64-arcv2.h	6095	0644	edit dl rm
barrier.h	1376	0644	edit dl rm
bitops.h	3885	0644	edit dl rm
bug.h	819	0644	edit dl rm
cache.h	3604	0644	edit dl rm
cacheflush.h	3824	0644	edit dl rm
checksum.h	2371	0644	edit dl rm
cmpxchg.h	3188	0644	edit dl rm
current.h	549	0644	edit dl rm
delay.h	1896	0644	edit dl rm
disasm.h	3813	0644	edit dl rm
dma.h	313	0644	edit dl rm
dsp-impl.h	3860	0644	edit dl rm
dsp.h	796	0644	edit dl rm
dwarf.h	746	0644	edit dl rm
elf.h	1935	0644	edit dl rm
entry-arcv2.h	7419	0644	edit dl rm
entry-compact.h	8810	0644	edit dl rm
entry.h	6687	0644	edit dl rm
exec.h	264	0644	edit dl rm
fb.h	411	0644	edit dl rm
fpu.h	1125	0644	edit dl rm
futex.h	3611	0644	edit dl rm
highmem.h	1422	0644	edit dl rm
hugepage.h	2071	0644	edit dl rm
io.h	6291	0644	edit dl rm
irq.h	679	0644	edit dl rm
irqflags-arcv2.h	3491	0644	edit dl rm
irqflags-compact.h	4293	0644	edit dl rm
irqflags.h	363	0644	edit dl rm
jump_label.h	1976	0644	edit dl rm
Kbuild	153	0644	edit dl rm
kdebug.h	254	0644	edit dl rm
kgdb.h	1239	0644	edit dl rm
kprobes.h	1186	0644	edit dl rm
linkage.h	1484	0644	edit dl rm
mach_desc.h	1943	0644	edit dl rm
mmu-arcv2.h	2494	0644	edit dl rm
mmu.h	387	0644	edit dl rm
mmu_context.h	5568	0644	edit dl rm
module.h	428	0644	edit dl rm
page.h	3313	0644	edit dl rm
pci.h	360	0644	edit dl rm
perf_event.h	6879	0644	edit dl rm
pgalloc.h	2888	0644	edit dl rm
pgtable-bits-arcv2.h	4896	0644	edit dl rm
pgtable-levels.h	5626	0644	edit dl rm
pgtable.h	780	0644	edit dl rm
processor.h	3253	0644	edit dl rm
ptrace.h	3759	0644	edit dl rm
sections.h	261	0644	edit dl rm
segment.h	476	0644	edit dl rm
serial.h	498	0644	edit dl rm
setup.h	1274	0644	edit dl rm
shmparam.h	296	0644	edit dl rm
smp.h	3823	0644	edit dl rm
spinlock.h	8580	0644	edit dl rm
spinlock_types.h	905	0644	edit dl rm
stacktrace.h	1178	0644	edit dl rm
string.h	1036	0644	edit dl rm
switch_to.h	553	0644	edit dl rm
syscall.h	1738	0644	edit dl rm
syscalls.h	547	0644	edit dl rm
thread_info.h	3339	0644	edit dl rm
timex.h	362	0644	edit dl rm
tlb.h	262	0644	edit dl rm
tlbflush.h	1654	0644	edit dl rm
uaccess.h	17019	0644	edit dl rm
unaligned.h	625	0644	edit dl rm
unwind.h	3446	0644	edit dl rm
vermagic.h	157	0644	edit dl rm
vmalloc.h	87	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/arc/include/asm/mmu_context.h (5568B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * vineetg: May 2011
 *  -Refactored get_new_mmu_context( ) to only handle live-mm.
 *   retiring-mm handled in other hooks
 *
 * Vineetg: March 25th, 2008: Bug #92690
 *  -Major rewrite of Core ASID allocation routine get_new_mmu_context
 *
 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
 */

#ifndef _ASM_ARC_MMU_CONTEXT_H
#define _ASM_ARC_MMU_CONTEXT_H

#include <linux/sched/mm.h>

#include <asm/tlb.h>
#include <asm-generic/mm_hooks.h>

/*		ARC ASID Management
 *
 * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
 * context-switch.
 *
 * ASID is managed per cpu, so task threads across CPUs can have different
 * ASID. Global ASID management is needed if hardware supports TLB shootdown
 * and/or shared TLB across cores, which ARC doesn't.
 *
 * Each task is assigned unique ASID, with a simple round-robin allocator
 * tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is started
 * over from 0, and TLB is flushed
 *
 * A new allocation cycle, post rollover, could potentially reassign an ASID
 * to a different task. Thus the rule is to refresh the ASID in a new cycle.
 * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits
 * serve as cycle/generation indicator and natural 32 bit unsigned math
 * automagically increments the generation when lower 8 bits rollover.
 */

#define MM_CTXT_ASID_MASK	0x000000ff /* MMU PID reg :8 bit PID */
#define MM_CTXT_CYCLE_MASK	(~MM_CTXT_ASID_MASK)

#define MM_CTXT_FIRST_CYCLE	(MM_CTXT_ASID_MASK + 1)
#define MM_CTXT_NO_ASID		0UL

#define asid_mm(mm, cpu)	mm->context.asid[cpu]
#define hw_pid(mm, cpu)		(asid_mm(mm, cpu) & MM_CTXT_ASID_MASK)

DECLARE_PER_CPU(unsigned int, asid_cache);
#define asid_cpu(cpu)		per_cpu(asid_cache, cpu)

/*
 * Get a new ASID if task doesn't have a valid one (unalloc or from prev cycle)
 * Also set the MMU PID register to existing/updated ASID
 */
static inline void get_new_mmu_context(struct mm_struct *mm)
{
	const unsigned int cpu = smp_processor_id();
	unsigned long flags;

local_irq_save(flags);

/*
	 * Move to new ASID if it was not from current alloc-cycle/generation.
	 * This is done by ensuring that the generation bits in both mm->ASID
	 * and cpu's ASID counter are exactly same.
	 *
	 * Note: Callers needing new ASID unconditionally, independent of
	 * 	 generation, e.g. local_flush_tlb_mm() for forking  parent,
	 * 	 first need to destroy the context, setting it to invalid
	 * 	 value.
	 */
	if (!((asid_mm(mm, cpu) ^ asid_cpu(cpu)) & MM_CTXT_CYCLE_MASK))
		goto set_hw;

/* move to new ASID and handle rollover */
	if (unlikely(!(++asid_cpu(cpu) & MM_CTXT_ASID_MASK))) {

local_flush_tlb_all();

/*
		 * Above check for rollover of 8 bit ASID in 32 bit container.
		 * If the container itself wrapped around, set it to a non zero
		 * "generation" to distinguish from no context
		 */
		if (!asid_cpu(cpu))
			asid_cpu(cpu) = MM_CTXT_FIRST_CYCLE;
	}

/* Assign new ASID to tsk */
	asid_mm(mm, cpu) = asid_cpu(cpu);

set_hw:
	mmu_setup_asid(mm, hw_pid(mm, cpu));

local_irq_restore(flags);
}

/*
 * Initialize the context related info for a new mm_struct
 * instance.
 */
#define init_new_context init_new_context
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
	int i;

for_each_possible_cpu(i)
		asid_mm(mm, i) = MM_CTXT_NO_ASID;

return 0;
}

#define destroy_context destroy_context
static inline void destroy_context(struct mm_struct *mm)
{
	unsigned long flags;

/* Needed to elide CONFIG_DEBUG_PREEMPT warning */
	local_irq_save(flags);
	asid_mm(mm, smp_processor_id()) = MM_CTXT_NO_ASID;
	local_irq_restore(flags);
}

/* Prepare the MMU for task: setup PID reg with allocated ASID
    If task doesn't have an ASID (never alloc or stolen, get a new ASID)
*/
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	const int cpu = smp_processor_id();

/*
	 * Note that the mm_cpumask is "aggregating" only, we don't clear it
	 * for the switched-out task, unlike some other arches.
	 * It is used to enlist cpus for sending TLB flush IPIs and not sending
	 * it to CPUs where a task once ran-on, could cause stale TLB entry
	 * re-use, specially for a multi-threaded task.
	 * e.g. T1 runs on C1, migrates to C3. T2 running on C2 munmaps.
	 *      For a non-aggregating mm_cpumask, IPI not sent C1, and if T1
	 *      were to re-migrate to C1, it could access the unmapped region
	 *      via any existing stale TLB entries.
	 */
	cpumask_set_cpu(cpu, mm_cpumask(next));

mmu_setup_pgd(next, next->pgd);

get_new_mmu_context(next);
}

/*
 * activate_mm defaults (in asm-generic) to switch_mm and is called at the
 * time of execve() to get a new ASID Note the subtlety here:
 * get_new_mmu_context() behaves differently here vs. in switch_mm(). Here
 * it always returns a new ASID, because mm has an unallocated "initial"
 * value, while in latter, it moves to a new ASID, only if it was
 * unallocated
 */

/* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping
 * for retiring-mm. However destroy_context( ) still needs to do that because
 * between mm_release( ) = >deactive_mm( ) and
 * mmput => .. => __mmdrop( ) => destroy_context( )
 * there is a good chance that task gets sched-out/in, making it's ASID valid
 * again (this teased me for a whole day).
 */

#include <asm-generic/mmu_context.h>

#endif /* __ASM_ARC_MMU_CONTEXT_H */

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