FM / asm

/usr/src/linux-headers-5.15.0-181/arch/arm64/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/arm64/include/asm

Name	Size	Mode	Actions
vdso/	-	0755	rm
xen/	-	0755	rm
acenv.h	395	0644	edit dl rm
acpi.h	4942	0644	edit dl rm
alternative-macros.h	5537	0644	edit dl rm
alternative.h	1013	0644	edit dl rm
archrandom.h	3121	0644	edit dl rm
arch_gicv3.h	4055	0644	edit dl rm
arch_timer.h	4631	0644	edit dl rm
arm-cci.h	254	0644	edit dl rm
arm_dsu_pmu.h	3007	0644	edit dl rm
asm-bug.h	952	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	958	0644	edit dl rm
asm-uaccess.h	2296	0644	edit dl rm
asm_pointer_auth.h	2432	0644	edit dl rm
assembler.h	21164	0644	edit dl rm
atomic.h	8618	0644	edit dl rm
atomic_ll_sc.h	10254	0644	edit dl rm
atomic_lse.h	11233	0644	edit dl rm
barrier.h	5429	0644	edit dl rm
bitops.h	850	0644	edit dl rm
bitrev.h	452	0644	edit dl rm
boot.h	369	0644	edit dl rm
brk-imm.h	889	0644	edit dl rm
bug.h	572	0644	edit dl rm
cache.h	3248	0644	edit dl rm
cacheflush.h	4873	0644	edit dl rm
checksum.h	1088	0644	edit dl rm
clocksource.h	136	0644	edit dl rm
cmpxchg.h	8057	0644	edit dl rm
compat.h	3919	0644	edit dl rm
compiler.h	1309	0644	edit dl rm
cpu.h	1520	0644	edit dl rm
cpufeature.h	29001	0644	edit dl rm
cpuidle.h	1330	0644	edit dl rm
cputype.h	11804	0644	edit dl rm
cpu_ops.h	2409	0644	edit dl rm
current.h	517	0644	edit dl rm
daifflags.h	3533	0644	edit dl rm
dcc.h	981	0644	edit dl rm
debug-monitors.h	3284	0644	edit dl rm
device.h	189	0644	edit dl rm
dmi.h	850	0644	edit dl rm
efi.h	4494	0644	edit dl rm
el2_setup.h	5363	0644	edit dl rm
elf.h	8196	0644	edit dl rm
esr.h	12549	0644	edit dl rm
exception.h	3015	0644	edit dl rm
exec.h	278	0644	edit dl rm
extable.h	1127	0644	edit dl rm
fb.h	460	0644	edit dl rm
fixmap.h	3099	0644	edit dl rm
fpsimd.h	5490	0644	edit dl rm
fpsimdmacros.h	6004	0644	edit dl rm
ftrace.h	2962	0644	edit dl rm
futex.h	2953	0644	edit dl rm
hardirq.h	2335	0644	edit dl rm
hugetlb.h	1920	0644	edit dl rm
hwcap.h	5207	0644	edit dl rm
hw_breakpoint.h	4091	0644	edit dl rm
hyperv-tlfs.h	2077	0644	edit dl rm
hypervisor.h	228	0644	edit dl rm
hyp_image.h	1911	0644	edit dl rm
image.h	1509	0644	edit dl rm
insn-def.h	571	0644	edit dl rm
insn.h	21884	0644	edit dl rm
io.h	6631	0644	edit dl rm
irq.h	395	0644	edit dl rm
irqflags.h	2933	0644	edit dl rm
irq_work.h	192	0644	edit dl rm
jump_label.h	1195	0644	edit dl rm
kasan.h	1568	0644	edit dl rm
Kbuild	186	0644	edit dl rm
kernel-pgtable.h	5023	0644	edit dl rm
kexec.h	2795	0644	edit dl rm
kfence.h	410	0644	edit dl rm
kgdb.h	3346	0644	edit dl rm
kprobes.h	1063	0644	edit dl rm
kvm_arm.h	12619	0644	edit dl rm
kvm_asm.h	9921	0644	edit dl rm
kvm_emulate.h	12462	0644	edit dl rm
kvm_host.h	25912	0644	edit dl rm
kvm_hyp.h	4389	0644	edit dl rm
kvm_mmu.h	8874	0644	edit dl rm
kvm_mte.h	1378	0644	edit dl rm
kvm_pgtable.h	19676	0644	edit dl rm
kvm_ptrauth.h	3543	0644	edit dl rm
kvm_ras.h	603	0644	edit dl rm
kvm_types.h	185	0644	edit dl rm
linkage.h	1751	0644	edit dl rm
lse.h	1267	0644	edit dl rm
memory.h	11838	0644	edit dl rm
mman.h	2699	0644	edit dl rm
mmu.h	2476	0644	edit dl rm
mmu_context.h	6944	0644	edit dl rm
mmzone.h	266	0644	edit dl rm
module.h	1810	0644	edit dl rm
module.lds.h	646	0644	edit dl rm
mshyperv.h	1387	0644	edit dl rm
mte-def.h	505	0644	edit dl rm
mte-kasan.h	3640	0644	edit dl rm
mte.h	3426	0644	edit dl rm
neon-intrinsics.h	959	0644	edit dl rm
neon.h	385	0644	edit dl rm
numa.h	165	0644	edit dl rm
page-def.h	441	0644	edit dl rm
page.h	1365	0644	edit dl rm
paravirt.h	580	0644	edit dl rm
patching.h	370	0644	edit dl rm
pci.h	764	0644	edit dl rm
percpu.h	8175	0644	edit dl rm
perf_event.h	10785	0644	edit dl rm
pgalloc.h	2269	0644	edit dl rm
pgtable-hwdef.h	10167	0644	edit dl rm
pgtable-prot.h	4302	0644	edit dl rm
pgtable-types.h	1305	0644	edit dl rm
pgtable.h	29965	0644	edit dl rm
pointer_auth.h	4651	0644	edit dl rm
preempt.h	2366	0644	edit dl rm
probes.h	650	0644	edit dl rm
proc-fns.h	562	0644	edit dl rm
processor.h	10002	0644	edit dl rm
ptdump.h	889	0644	edit dl rm
ptrace.h	10539	0644	edit dl rm
pvclock-abi.h	374	0644	edit dl rm
rwonce.h	2009	0644	edit dl rm
scs.h	497	0644	edit dl rm
sdei.h	1967	0644	edit dl rm
seccomp.h	870	0644	edit dl rm
sections.h	1099	0644	edit dl rm
setup.h	195	0644	edit dl rm
set_memory.h	487	0644	edit dl rm
shmparam.h	425	0644	edit dl rm
signal.h	650	0644	edit dl rm
signal32.h	1980	0644	edit dl rm
simd.h	1488	0644	edit dl rm
smp.h	3955	0644	edit dl rm
smp_plat.h	824	0644	edit dl rm
sparsemem.h	682	0644	edit dl rm
spectre.h	3000	0644	edit dl rm
spinlock.h	601	0644	edit dl rm
spinlock_types.h	360	0644	edit dl rm
stackprotector.h	1359	0644	edit dl rm
stacktrace.h	4314	0644	edit dl rm
stack_pointer.h	247	0644	edit dl rm
stage2_pgtable.h	1058	0644	edit dl rm
stat.h	947	0644	edit dl rm
string.h	1972	0644	edit dl rm
suspend.h	1694	0644	edit dl rm
sync_bitops.h	1085	0644	edit dl rm
syscall.h	2146	0644	edit dl rm
syscall_wrapper.h	3120	0644	edit dl rm
sysreg.h	45773	0644	edit dl rm
system_misc.h	880	0644	edit dl rm
thread_info.h	3887	0644	edit dl rm
timex.h	343	0644	edit dl rm
tlb.h	2332	0644	edit dl rm
tlbflush.h	11891	0644	edit dl rm
topology.h	1203	0644	edit dl rm
trans_pgd.h	1036	0644	edit dl rm
traps.h	2909	0644	edit dl rm
uaccess.h	13718	0644	edit dl rm
unistd.h	1361	0644	edit dl rm
unistd32.h	31568	0644	edit dl rm
uprobes.h	579	0644	edit dl rm
vdso.h	631	0644	edit dl rm
vectors.h	1775	0644	edit dl rm
vermagic.h	200	0644	edit dl rm
virt.h	3569	0644	edit dl rm
vmalloc.h	694	0644	edit dl rm
vmap_stack.h	703	0644	edit dl rm
word-at-a-time.h	1797	0644	edit dl rm
xor.h	1668	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/arm64/include/asm/cache.h (3248B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012 ARM Ltd.
 */
#ifndef __ASM_CACHE_H
#define __ASM_CACHE_H

#include <asm/cputype.h>

#define CTR_L1IP_SHIFT		14
#define CTR_L1IP_MASK		3
#define CTR_DMINLINE_SHIFT	16
#define CTR_IMINLINE_SHIFT	0
#define CTR_IMINLINE_MASK	0xf
#define CTR_ERG_SHIFT		20
#define CTR_CWG_SHIFT		24
#define CTR_CWG_MASK		15
#define CTR_IDC_SHIFT		28
#define CTR_DIC_SHIFT		29

#define CTR_CACHE_MINLINE_MASK	\
	(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)

#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)

#define ICACHE_POLICY_VPIPT	0
#define ICACHE_POLICY_RESERVED	1
#define ICACHE_POLICY_VIPT	2
#define ICACHE_POLICY_PIPT	3

#define L1_CACHE_SHIFT		(6)
#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#define CLIDR_LOUU_SHIFT	27
#define CLIDR_LOC_SHIFT		24
#define CLIDR_LOUIS_SHIFT	21

#define CLIDR_LOUU(clidr)	(((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
#define CLIDR_LOC(clidr)	(((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
#define CLIDR_LOUIS(clidr)	(((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)

/*
 * Memory returned by kmalloc() may be used for DMA, so we must make
 * sure that all such allocations are cache aligned. Otherwise,
 * unrelated code may cause parts of the buffer to be read into the
 * cache before the transfer is done, causing old data to be seen by
 * the CPU.
 */
#define ARCH_DMA_MINALIGN	(128)

#ifdef CONFIG_KASAN_SW_TAGS
#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)
#elif defined(CONFIG_KASAN_HW_TAGS)
#define ARCH_SLAB_MINALIGN	MTE_GRANULE_SIZE
#endif

#ifndef __ASSEMBLY__

#include <linux/bitops.h>

#define ICACHEF_ALIASING	0
#define ICACHEF_VPIPT		1
extern unsigned long __icache_flags;

/*
 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
 * permitted in the I-cache.
 */
static inline int icache_is_aliasing(void)
{
	return test_bit(ICACHEF_ALIASING, &__icache_flags);
}

static __always_inline int icache_is_vpipt(void)
{
	return test_bit(ICACHEF_VPIPT, &__icache_flags);
}

static inline u32 cache_type_cwg(void)
{
	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
}

#define __read_mostly __section(".data..read_mostly")

static inline int cache_line_size_of_cpu(void)
{
	u32 cwg = cache_type_cwg();

return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
}

int cache_line_size(void);

/*
 * Read the effective value of CTR_EL0.
 *
 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
 * section D10.2.33 "CTR_EL0, Cache Type Register" :
 *
 * CTR_EL0.IDC reports the data cache clean requirements for
 * instruction to data coherence.
 *
 *  0 - dcache clean to PoU is required unless :
 *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
 *  1 - dcache clean to PoU is not required for i-to-d coherence.
 *
 * This routine provides the CTR_EL0 with the IDC field updated to the
 * effective state.
 */
static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
{
	u32 ctr = read_cpuid_cachetype();

if (!(ctr & BIT(CTR_IDC_SHIFT))) {
		u64 clidr = read_sysreg(clidr_el1);

if (CLIDR_LOC(clidr) == 0 ||
		    (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
			ctr |= BIT(CTR_IDC_SHIFT);
	}

return ctr;
}

#endif	/* __ASSEMBLY__ */

#endif

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