FM / asm

/usr/src/linux-headers-5.15.0-181/arch/hexagon/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/hexagon/include/asm

Name	Size	Mode	Actions
asm-offsets.h	35	0644	edit dl rm
atomic.h	4361	0644	edit dl rm
bitops.h	6152	0644	edit dl rm
cache.h	555	0644	edit dl rm
cacheflush.h	2725	0644	edit dl rm
checksum.h	685	0644	edit dl rm
cmpxchg.h	2003	0644	edit dl rm
delay.h	344	0644	edit dl rm
dma.h	300	0644	edit dl rm
elf.h	5758	0644	edit dl rm
exec.h	398	0644	edit dl rm
fixmap.h	369	0644	edit dl rm
fpu.h	90	0644	edit dl rm
futex.h	2306	0644	edit dl rm
hexagon_vm.h	5909	0644	edit dl rm
intrinsics.h	369	0644	edit dl rm
io.h	6264	0644	edit dl rm
irq.h	523	0644	edit dl rm
irqflags.h	860	0644	edit dl rm
Kbuild	131	0644	edit dl rm
kgdb.h	754	0644	edit dl rm
linkage.h	237	0644	edit dl rm
mem-layout.h	2865	0644	edit dl rm
mmu.h	490	0644	edit dl rm
mmu_context.h	1544	0644	edit dl rm
page.h	4179	0644	edit dl rm
perf_event.h	207	0644	edit dl rm
pgalloc.h	2709	0644	edit dl rm
pgtable.h	11952	0644	edit dl rm
processor.h	3173	0644	edit dl rm
smp.h	707	0644	edit dl rm
spinlock.h	3295	0644	edit dl rm
spinlock_types.h	545	0644	edit dl rm
string.h	472	0644	edit dl rm
suspend.h	238	0644	edit dl rm
switch_to.h	478	0644	edit dl rm
syscall.h	1170	0644	edit dl rm
syscalls.h	204	0644	edit dl rm
thread_info.h	3505	0644	edit dl rm
time.h	346	0644	edit dl rm
timex.h	495	0644	edit dl rm
tlb.h	253	0644	edit dl rm
tlbflush.h	1497	0644	edit dl rm
traps.h	410	0644	edit dl rm
uaccess.h	1870	0644	edit dl rm
vdso.h	307	0644	edit dl rm
vermagic.h	299	0644	edit dl rm
vmalloc.h	99	0644	edit dl rm
vm_fault.h	359	0644	edit dl rm
vm_mmu.h	2818	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/hexagon/include/asm/atomic.h (4361B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Atomic operations for the Hexagon architecture
 *
 * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
 */

#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H

#include <linux/types.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>

/*  Normal writes in our arch don't clear lock reservations  */

static inline void arch_atomic_set(atomic_t *v, int new)
{
	asm volatile(
		"1:	r6 = memw_locked(%0);\n"
		"	memw_locked(%0,p0) = %1;\n"
		"	if (!P0) jump 1b;\n"
		:
		: "r" (&v->counter), "r" (new)
		: "memory", "p0", "r6"
	);
}

#define arch_atomic_set_release(v, i)	arch_atomic_set((v), (i))

/**
 * arch_atomic_read - reads a word, atomically
 * @v: pointer to atomic value
 *
 * Assumes all word reads on our architecture are atomic.
 */
#define arch_atomic_read(v)		READ_ONCE((v)->counter)

/**
 * arch_atomic_xchg - atomic
 * @v: pointer to memory to change
 * @new: new value (technically passed in a register -- see xchg)
 */
#define arch_atomic_xchg(v, new)	(arch_xchg(&((v)->counter), (new)))

/**
 * arch_atomic_cmpxchg - atomic compare-and-exchange values
 * @v: pointer to value to change
 * @old:  desired old value to match
 * @new:  new value to put in
 *
 * Parameters are then pointer, value-in-register, value-in-register,
 * and the output is the old value.
 *
 * Apparently this is complicated for archs that don't support
 * the memw_locked like we do (or it's broken or whatever).
 *
 * Kind of the lynchpin of the rest of the generically defined routines.
 * Remember V2 had that bug with dotnew predicate set by memw_locked.
 *
 * "old" is "expected" old val, __oldval is actual old value
 */
static inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
{
	int __oldval;

asm volatile(
		"1:	%0 = memw_locked(%1);\n"
		"	{ P0 = cmp.eq(%0,%2);\n"
		"	  if (!P0.new) jump:nt 2f; }\n"
		"	memw_locked(%1,P0) = %3;\n"
		"	if (!P0) jump 1b;\n"
		"2:\n"
		: "=&r" (__oldval)
		: "r" (&v->counter), "r" (old), "r" (new)
		: "memory", "p0"
	);

return __oldval;
}

#define ATOMIC_OP(op)							\
static inline void arch_atomic_##op(int i, atomic_t *v)			\
{									\
	int output;							\
									\
	__asm__ __volatile__ (						\
		"1:	%0 = memw_locked(%1);\n"			\
		"	%0 = "#op "(%0,%2);\n"				\
		"	memw_locked(%1,P3)=%0;\n"			\
		"	if (!P3) jump 1b;\n"				\
		: "=&r" (output)					\
		: "r" (&v->counter), "r" (i)				\
		: "memory", "p3"					\
	);								\
}									\

#define ATOMIC_OP_RETURN(op)						\
static inline int arch_atomic_##op##_return(int i, atomic_t *v)		\
{									\
	int output;							\
									\
	__asm__ __volatile__ (						\
		"1:	%0 = memw_locked(%1);\n"			\
		"	%0 = "#op "(%0,%2);\n"				\
		"	memw_locked(%1,P3)=%0;\n"			\
		"	if (!P3) jump 1b;\n"				\
		: "=&r" (output)					\
		: "r" (&v->counter), "r" (i)				\
		: "memory", "p3"					\
	);								\
	return output;							\
}

#define ATOMIC_FETCH_OP(op)						\
static inline int arch_atomic_fetch_##op(int i, atomic_t *v)		\
{									\
	int output, val;						\
									\
	__asm__ __volatile__ (						\
		"1:	%0 = memw_locked(%2);\n"			\
		"	%1 = "#op "(%0,%3);\n"				\
		"	memw_locked(%2,P3)=%1;\n"			\
		"	if (!P3) jump 1b;\n"				\
		: "=&r" (output), "=&r" (val)				\
		: "r" (&v->counter), "r" (i)				\
		: "memory", "p3"					\
	);								\
	return output;							\
}

#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)

ATOMIC_OPS(add)
ATOMIC_OPS(sub)

#undef ATOMIC_OPS
#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)

ATOMIC_OPS(and)
ATOMIC_OPS(or)
ATOMIC_OPS(xor)

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

/**
 * arch_atomic_fetch_add_unless - add unless the number is a given value
 * @v: pointer to value
 * @a: amount to add
 * @u: unless value is equal to u
 *
 * Returns old value.
 *
 */

static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
{
	int __oldval;
	register int tmp;

asm volatile(
		"1:	%0 = memw_locked(%2);"
		"	{"
		"		p3 = cmp.eq(%0, %4);"
		"		if (p3.new) jump:nt 2f;"
		"		%1 = add(%0, %3);"
		"	}"
		"	memw_locked(%2, p3) = %1;"
		"	{"
		"		if (!p3) jump 1b;"
		"	}"
		"2:"
		: "=&r" (__oldval), "=&r" (tmp)
		: "r" (v), "r" (a), "r" (u)
		: "memory", "p3"
	);
	return __oldval;
}
#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless

#endif

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