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/usr/src/linux-headers-5.15.0-181/arch/hexagon/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/hexagon/include/asm

Name	Size	Mode	Actions
asm-offsets.h	35	0644	edit dl rm
atomic.h	4361	0644	edit dl rm
bitops.h	6152	0644	edit dl rm
cache.h	555	0644	edit dl rm
cacheflush.h	2725	0644	edit dl rm
checksum.h	685	0644	edit dl rm
cmpxchg.h	2003	0644	edit dl rm
delay.h	344	0644	edit dl rm
dma.h	300	0644	edit dl rm
elf.h	5758	0644	edit dl rm
exec.h	398	0644	edit dl rm
fixmap.h	369	0644	edit dl rm
fpu.h	90	0644	edit dl rm
futex.h	2306	0644	edit dl rm
hexagon_vm.h	5909	0644	edit dl rm
intrinsics.h	369	0644	edit dl rm
io.h	6264	0644	edit dl rm
irq.h	523	0644	edit dl rm
irqflags.h	860	0644	edit dl rm
Kbuild	131	0644	edit dl rm
kgdb.h	754	0644	edit dl rm
linkage.h	237	0644	edit dl rm
mem-layout.h	2865	0644	edit dl rm
mmu.h	490	0644	edit dl rm
mmu_context.h	1544	0644	edit dl rm
page.h	4179	0644	edit dl rm
perf_event.h	207	0644	edit dl rm
pgalloc.h	2709	0644	edit dl rm
pgtable.h	11952	0644	edit dl rm
processor.h	3173	0644	edit dl rm
smp.h	707	0644	edit dl rm
spinlock.h	3295	0644	edit dl rm
spinlock_types.h	545	0644	edit dl rm
string.h	472	0644	edit dl rm
suspend.h	238	0644	edit dl rm
switch_to.h	478	0644	edit dl rm
syscall.h	1170	0644	edit dl rm
syscalls.h	204	0644	edit dl rm
thread_info.h	3505	0644	edit dl rm
time.h	346	0644	edit dl rm
timex.h	495	0644	edit dl rm
tlb.h	253	0644	edit dl rm
tlbflush.h	1497	0644	edit dl rm
traps.h	410	0644	edit dl rm
uaccess.h	1870	0644	edit dl rm
vdso.h	307	0644	edit dl rm
vermagic.h	299	0644	edit dl rm
vmalloc.h	99	0644	edit dl rm
vm_fault.h	359	0644	edit dl rm
vm_mmu.h	2818	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/hexagon/include/asm/cacheflush.h (2725B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Cache flush operations for the Hexagon architecture
 *
 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
 */

#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H

#include <linux/mm_types.h>

/* Cache flushing:
 *
 *  - flush_cache_all() flushes entire cache
 *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
 *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
 *  - flush_cache_range(vma, start, end) flushes a range of pages
 *  - flush_icache_range(start, end) flush a range of instructions
 *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
 *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
 *
 *  Need to doublecheck which one is really needed for ptrace stuff to work.
 */
#define LINESIZE	32
#define LINEBITS	5

/*
 * Flush Dcache range through current map.
 */
extern void flush_dcache_range(unsigned long start, unsigned long end);
#define flush_dcache_range flush_dcache_range

/*
 * Flush Icache range through current map.
 */
extern void flush_icache_range(unsigned long start, unsigned long end);
#define flush_icache_range flush_icache_range

/*
 * Memory-management related flushes are there to ensure in non-physically
 * indexed cache schemes that stale lines belonging to a given ASID aren't
 * in the cache to confuse things.  The prototype Hexagon Virtual Machine
 * only uses a single ASID for all user-mode maps, which should
 * mean that they aren't necessary.  A brute-force, flush-everything
 * implementation, with the name xxxxx_hexagon() is present in
 * arch/hexagon/mm/cache.c, but let's not wire it up until we know
 * it is needed.
 */
extern void flush_cache_all_hexagon(void);

/*
 * This may or may not ever have to be non-null, depending on the
 * virtual machine MMU.  For a native kernel, it's definitiely  a no-op
 *
 * This is also the place where deferred cache coherency stuff seems
 * to happen, classically...  but instead we do it like ia64 and
 * clean the cache when the PTE is set.
 *
 */
static inline void update_mmu_cache(struct vm_area_struct *vma,
					unsigned long address, pte_t *ptep)
{
	/*  generic_ptrace_pokedata doesn't wind up here, does it?  */
}

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long vaddr, void *dst, void *src, int len);
#define copy_to_user_page copy_to_user_page

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy(dst, src, len)

extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);

#include <asm-generic/cacheflush.h>

#endif

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