FM / asm

/usr/src/linux-headers-5.15.0-181/arch/ia64/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/ia64/include/asm

Name	Size	Mode	Actions
native/	-	0755	rm
sn/	-	0755	rm
uv/	-	0755	rm
acenv.h	1153	0644	edit dl rm
acpi-ext.h	444	0644	edit dl rm
acpi.h	2772	0644	edit dl rm
agp.h	863	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	892	0644	edit dl rm
asmmacro.h	3372	0644	edit dl rm
atomic.h	6390	0644	edit dl rm
barrier.h	2414	0644	edit dl rm
bitops.h	11112	0644	edit dl rm
bug.h	404	0644	edit dl rm
cache.h	752	0644	edit dl rm
cacheflush.h	903	0644	edit dl rm
checksum.h	1746	0644	edit dl rm
clocksource.h	276	0644	edit dl rm
cmpxchg.h	479	0644	edit dl rm
cpu.h	456	0644	edit dl rm
cputime.h	648	0644	edit dl rm
current.h	418	0644	edit dl rm
cyclone.h	442	0644	edit dl rm
delay.h	1738	0644	edit dl rm
device.h	236	0644	edit dl rm
div64.h	31	0644	edit dl rm
dma-mapping.h	382	0644	edit dl rm
dma.h	351	0644	edit dl rm
dmi.h	343	0644	edit dl rm
early_ioremap.h	428	0644	edit dl rm
efi.h	374	0644	edit dl rm
elf.h	10025	0644	edit dl rm
emergency-restart.h	149	0644	edit dl rm
esi.h	887	0644	edit dl rm
exception.h	609	0644	edit dl rm
export.h	115	0644	edit dl rm
extable.h	330	0644	edit dl rm
fb.h	569	0644	edit dl rm
fpswa.h	1925	0644	edit dl rm
ftrace.h	748	0644	edit dl rm
futex.h	2616	0644	edit dl rm
gcc_intrin.h	368	0644	edit dl rm
hardirq.h	561	0644	edit dl rm
hugetlb.h	933	0644	edit dl rm
hw_irq.h	5776	0644	edit dl rm
idle.h	200	0644	edit dl rm
intrinsics.h	306	0644	edit dl rm
io.h	7527	0644	edit dl rm
iommu.h	505	0644	edit dl rm
iommu_table.h	175	0644	edit dl rm
iosapic.h	2752	0644	edit dl rm
irq.h	960	0644	edit dl rm
irqflags.h	2096	0644	edit dl rm
irq_regs.h	34	0644	edit dl rm
irq_remapping.h	142	0644	edit dl rm
Kbuild	139	0644	edit dl rm
kdebug.h	1011	0644	edit dl rm
kexec.h	1606	0644	edit dl rm
kprobes.h	3148	0644	edit dl rm
kregs.h	6890	0644	edit dl rm
libata-portmap.h	225	0644	edit dl rm
linkage.h	398	0644	edit dl rm
local.h	31	0644	edit dl rm
mca.h	6009	0644	edit dl rm
mca_asm.h	7356	0644	edit dl rm
meminit.h	1751	0644	edit dl rm
mman.h	432	0644	edit dl rm
mmiowb.h	433	0644	edit dl rm
mmu.h	374	0644	edit dl rm
mmu_context.h	5304	0644	edit dl rm
mmzone.h	869	0644	edit dl rm
module.h	1154	0644	edit dl rm
module.lds.h	394	0644	edit dl rm
msidef.h	1438	0644	edit dl rm
nodedata.h	1898	0644	edit dl rm
numa.h	2338	0644	edit dl rm
page.h	5856	0644	edit dl rm
pal.h	54674	0644	edit dl rm
param.h	439	0644	edit dl rm
parport.h	534	0644	edit dl rm
patch.h	1214	0644	edit dl rm
pci.h	2007	0644	edit dl rm
percpu.h	1354	0644	edit dl rm
pgalloc.h	1569	0644	edit dl rm
pgtable.h	19846	0644	edit dl rm
processor.h	17876	0644	edit dl rm
ptrace.h	5258	0644	edit dl rm
sal.h	27189	0644	edit dl rm
sections.h	1679	0644	edit dl rm
serial.h	446	0644	edit dl rm
shmparam.h	445	0644	edit dl rm
signal.h	749	0644	edit dl rm
smp.h	2514	0644	edit dl rm
sparsemem.h	785	0644	edit dl rm
spinlock.h	7149	0644	edit dl rm
spinlock_types.h	475	0644	edit dl rm
string.h	659	0644	edit dl rm
switch_to.h	2702	0644	edit dl rm
syscall.h	1820	0644	edit dl rm
termios.h	1923	0644	edit dl rm
thread_info.h	4906	0644	edit dl rm
timex.h	1502	0644	edit dl rm
tlb.h	1577	0644	edit dl rm
tlbflush.h	3165	0644	edit dl rm
topology.h	1408	0644	edit dl rm
types.h	828	0644	edit dl rm
uaccess.h	9730	0644	edit dl rm
uncached.h	314	0644	edit dl rm
unistd.h	987	0644	edit dl rm
unwind.h	5873	0644	edit dl rm
user.h	2299	0644	edit dl rm
ustack.h	403	0644	edit dl rm
vermagic.h	341	0644	edit dl rm
vga.h	649	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
xor.h	743	0644	edit dl rm
xtp.h	938	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/ia64/include/asm/kregs.h (6890B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_IA64_KREGS_H
#define _ASM_IA64_KREGS_H

/*
 * Copyright (C) 2001-2002 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 */
/*
 * This file defines the kernel register usage convention used by Linux/ia64.
 */

/*
 * Kernel registers:
 */
#define IA64_KR_IO_BASE		0	/* ar.k0: legacy I/O base address */
#define IA64_KR_TSSD		1	/* ar.k1: IVE uses this as the TSSD */
#define IA64_KR_PER_CPU_DATA	3	/* ar.k3: physical per-CPU base */
#define IA64_KR_CURRENT_STACK	4	/* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */
#define IA64_KR_FPU_OWNER	5	/* ar.k5: fpu-owner (UP only, at the moment) */
#define IA64_KR_CURRENT		6	/* ar.k6: "current" task pointer */
#define IA64_KR_PT_BASE		7	/* ar.k7: page table base address (physical) */

#define _IA64_KR_PASTE(x,y)	x##y
#define _IA64_KR_PREFIX(n)	_IA64_KR_PASTE(ar.k, n)
#define IA64_KR(n)		_IA64_KR_PREFIX(IA64_KR_##n)

/*
 * Translation registers:
 */
#define IA64_TR_KERNEL		0	/* itr0, dtr0: maps kernel image (code & data) */
#define IA64_TR_PALCODE		1	/* itr1: maps PALcode as required by EFI */
#define IA64_TR_CURRENT_STACK	1	/* dtr1: maps kernel's memory- & register-stacks */

#define IA64_TR_ALLOC_BASE	2 	/* itr&dtr: Base of dynamic TR resource*/
#define IA64_TR_ALLOC_MAX	64 	/* Max number for dynamic use*/

/* Processor status register bits: */
#define IA64_PSR_BE_BIT		1
#define IA64_PSR_UP_BIT		2
#define IA64_PSR_AC_BIT		3
#define IA64_PSR_MFL_BIT	4
#define IA64_PSR_MFH_BIT	5
#define IA64_PSR_IC_BIT		13
#define IA64_PSR_I_BIT		14
#define IA64_PSR_PK_BIT		15
#define IA64_PSR_DT_BIT		17
#define IA64_PSR_DFL_BIT	18
#define IA64_PSR_DFH_BIT	19
#define IA64_PSR_SP_BIT		20
#define IA64_PSR_PP_BIT		21
#define IA64_PSR_DI_BIT		22
#define IA64_PSR_SI_BIT		23
#define IA64_PSR_DB_BIT		24
#define IA64_PSR_LP_BIT		25
#define IA64_PSR_TB_BIT		26
#define IA64_PSR_RT_BIT		27
/* The following are not affected by save_flags()/restore_flags(): */
#define IA64_PSR_CPL0_BIT	32
#define IA64_PSR_CPL1_BIT	33
#define IA64_PSR_IS_BIT		34
#define IA64_PSR_MC_BIT		35
#define IA64_PSR_IT_BIT		36
#define IA64_PSR_ID_BIT		37
#define IA64_PSR_DA_BIT		38
#define IA64_PSR_DD_BIT		39
#define IA64_PSR_SS_BIT		40
#define IA64_PSR_RI_BIT		41
#define IA64_PSR_ED_BIT		43
#define IA64_PSR_BN_BIT		44
#define IA64_PSR_IA_BIT		45

/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
   execve().  Only list flags here that need to be cleared/set for BOTH clone2() and
   execve().  */
#define IA64_PSR_BITS_TO_CLEAR	(IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
				 IA64_PSR_TB  | IA64_PSR_ID  | IA64_PSR_DA | IA64_PSR_DD | \
				 IA64_PSR_SS  | IA64_PSR_ED  | IA64_PSR_IA)
#define IA64_PSR_BITS_TO_SET	(IA64_PSR_DFH | IA64_PSR_SP)

#define IA64_PSR_BE	(__IA64_UL(1) << IA64_PSR_BE_BIT)
#define IA64_PSR_UP	(__IA64_UL(1) << IA64_PSR_UP_BIT)
#define IA64_PSR_AC	(__IA64_UL(1) << IA64_PSR_AC_BIT)
#define IA64_PSR_MFL	(__IA64_UL(1) << IA64_PSR_MFL_BIT)
#define IA64_PSR_MFH	(__IA64_UL(1) << IA64_PSR_MFH_BIT)
#define IA64_PSR_IC	(__IA64_UL(1) << IA64_PSR_IC_BIT)
#define IA64_PSR_I	(__IA64_UL(1) << IA64_PSR_I_BIT)
#define IA64_PSR_PK	(__IA64_UL(1) << IA64_PSR_PK_BIT)
#define IA64_PSR_DT	(__IA64_UL(1) << IA64_PSR_DT_BIT)
#define IA64_PSR_DFL	(__IA64_UL(1) << IA64_PSR_DFL_BIT)
#define IA64_PSR_DFH	(__IA64_UL(1) << IA64_PSR_DFH_BIT)
#define IA64_PSR_SP	(__IA64_UL(1) << IA64_PSR_SP_BIT)
#define IA64_PSR_PP	(__IA64_UL(1) << IA64_PSR_PP_BIT)
#define IA64_PSR_DI	(__IA64_UL(1) << IA64_PSR_DI_BIT)
#define IA64_PSR_SI	(__IA64_UL(1) << IA64_PSR_SI_BIT)
#define IA64_PSR_DB	(__IA64_UL(1) << IA64_PSR_DB_BIT)
#define IA64_PSR_LP	(__IA64_UL(1) << IA64_PSR_LP_BIT)
#define IA64_PSR_TB	(__IA64_UL(1) << IA64_PSR_TB_BIT)
#define IA64_PSR_RT	(__IA64_UL(1) << IA64_PSR_RT_BIT)
/* The following are not affected by save_flags()/restore_flags(): */
#define IA64_PSR_CPL	(__IA64_UL(3) << IA64_PSR_CPL0_BIT)
#define IA64_PSR_IS	(__IA64_UL(1) << IA64_PSR_IS_BIT)
#define IA64_PSR_MC	(__IA64_UL(1) << IA64_PSR_MC_BIT)
#define IA64_PSR_IT	(__IA64_UL(1) << IA64_PSR_IT_BIT)
#define IA64_PSR_ID	(__IA64_UL(1) << IA64_PSR_ID_BIT)
#define IA64_PSR_DA	(__IA64_UL(1) << IA64_PSR_DA_BIT)
#define IA64_PSR_DD	(__IA64_UL(1) << IA64_PSR_DD_BIT)
#define IA64_PSR_SS	(__IA64_UL(1) << IA64_PSR_SS_BIT)
#define IA64_PSR_RI	(__IA64_UL(3) << IA64_PSR_RI_BIT)
#define IA64_PSR_ED	(__IA64_UL(1) << IA64_PSR_ED_BIT)
#define IA64_PSR_BN	(__IA64_UL(1) << IA64_PSR_BN_BIT)
#define IA64_PSR_IA	(__IA64_UL(1) << IA64_PSR_IA_BIT)

/* User mask bits: */
#define IA64_PSR_UM	(IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)

/* Default Control Register */
#define IA64_DCR_PP_BIT		 0	/* privileged performance monitor default */
#define IA64_DCR_BE_BIT		 1	/* big-endian default */
#define IA64_DCR_LC_BIT		 2	/* ia32 lock-check enable */
#define IA64_DCR_DM_BIT		 8	/* defer TLB miss faults */
#define IA64_DCR_DP_BIT		 9	/* defer page-not-present faults */
#define IA64_DCR_DK_BIT		10	/* defer key miss faults */
#define IA64_DCR_DX_BIT		11	/* defer key permission faults */
#define IA64_DCR_DR_BIT		12	/* defer access right faults */
#define IA64_DCR_DA_BIT		13	/* defer access bit faults */
#define IA64_DCR_DD_BIT		14	/* defer debug faults */

#define IA64_DCR_PP	(__IA64_UL(1) << IA64_DCR_PP_BIT)
#define IA64_DCR_BE	(__IA64_UL(1) << IA64_DCR_BE_BIT)
#define IA64_DCR_LC	(__IA64_UL(1) << IA64_DCR_LC_BIT)
#define IA64_DCR_DM	(__IA64_UL(1) << IA64_DCR_DM_BIT)
#define IA64_DCR_DP	(__IA64_UL(1) << IA64_DCR_DP_BIT)
#define IA64_DCR_DK	(__IA64_UL(1) << IA64_DCR_DK_BIT)
#define IA64_DCR_DX	(__IA64_UL(1) << IA64_DCR_DX_BIT)
#define IA64_DCR_DR	(__IA64_UL(1) << IA64_DCR_DR_BIT)
#define IA64_DCR_DA	(__IA64_UL(1) << IA64_DCR_DA_BIT)
#define IA64_DCR_DD	(__IA64_UL(1) << IA64_DCR_DD_BIT)

/* Interrupt Status Register */
#define IA64_ISR_X_BIT		32	/* execute access */
#define IA64_ISR_W_BIT		33	/* write access */
#define IA64_ISR_R_BIT		34	/* read access */
#define IA64_ISR_NA_BIT		35	/* non-access */
#define IA64_ISR_SP_BIT		36	/* speculative load exception */
#define IA64_ISR_RS_BIT		37	/* mandatory register-stack exception */
#define IA64_ISR_IR_BIT		38	/* invalid register frame exception */
#define IA64_ISR_CODE_MASK	0xf

#define IA64_ISR_X	(__IA64_UL(1) << IA64_ISR_X_BIT)
#define IA64_ISR_W	(__IA64_UL(1) << IA64_ISR_W_BIT)
#define IA64_ISR_R	(__IA64_UL(1) << IA64_ISR_R_BIT)
#define IA64_ISR_NA	(__IA64_UL(1) << IA64_ISR_NA_BIT)
#define IA64_ISR_SP	(__IA64_UL(1) << IA64_ISR_SP_BIT)
#define IA64_ISR_RS	(__IA64_UL(1) << IA64_ISR_RS_BIT)
#define IA64_ISR_IR	(__IA64_UL(1) << IA64_ISR_IR_BIT)

/* ISR code field for non-access instructions */
#define IA64_ISR_CODE_TPA	0
#define IA64_ISR_CODE_FC	1
#define IA64_ISR_CODE_PROBE	2
#define IA64_ISR_CODE_TAK	3
#define IA64_ISR_CODE_LFETCH	4
#define IA64_ISR_CODE_PROBEF	5

#endif /* _ASM_IA64_kREGS_H */

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