FM / asm

/usr/src/linux-headers-5.15.0-181/arch/m68k/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/m68k/include/asm

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adb_iop.h	1188	0644	edit dl rm
amigahw.h	10737	0644	edit dl rm
amigaints.h	3583	0644	edit dl rm
amigayle.h	3271	0644	edit dl rm
amipcmcia.h	2568	0644	edit dl rm
apollohw.h	2410	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	211	0644	edit dl rm
atarihw.h	20919	0644	edit dl rm
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atarikb.h	1434	0644	edit dl rm
atari_joystick.h	457	0644	edit dl rm
atari_stdma.h	514	0644	edit dl rm
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atomic.h	5016	0644	edit dl rm
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bootinfo.h	783	0644	edit dl rm
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bug.h	659	0644	edit dl rm
bvme6000hw.h	3529	0644	edit dl rm
cache.h	296	0644	edit dl rm
cacheflush.h	133	0644	edit dl rm
cacheflush_mm.h	7173	0644	edit dl rm
cacheflush_no.h	1884	0644	edit dl rm
checksum.h	3497	0644	edit dl rm
cmpxchg.h	3189	0644	edit dl rm
coldfire.h	1653	0644	edit dl rm
contregs.h	3390	0644	edit dl rm
current.h	580	0644	edit dl rm
delay.h	3504	0644	edit dl rm
div64.h	858	0644	edit dl rm
dma.h	17040	0644	edit dl rm
dsp56k.h	1269	0644	edit dl rm
dvma.h	9903	0644	edit dl rm
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entry.h	5902	0644	edit dl rm
export.h	53	0644	edit dl rm
fb.h	921	0644	edit dl rm
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flat.h	333	0644	edit dl rm
floppy.h	5330	0644	edit dl rm
fpu.h	535	0644	edit dl rm
ftrace.h	12	0644	edit dl rm
gpio.h	2294	0644	edit dl rm
hash.h	2115	0644	edit dl rm
hp300hw.h	186	0644	edit dl rm
hwtest.h	467	0644	edit dl rm
ide.h	1708	0644	edit dl rm
idprom.h	725	0644	edit dl rm
intersil.h	1134	0644	edit dl rm
io.h	244	0644	edit dl rm
io_mm.h	13198	0644	edit dl rm
io_no.h	4196	0644	edit dl rm
irq.h	2634	0644	edit dl rm
irqflags.h	1652	0644	edit dl rm
Kbuild	165	0644	edit dl rm
kexec.h	732	0644	edit dl rm
kmap.h	1754	0644	edit dl rm
linkage.h	1583	0644	edit dl rm
m52xxacr.h	3660	0644	edit dl rm
m53xxacr.h	3683	0644	edit dl rm
m53xxsim.h	55262	0644	edit dl rm
m54xxacr.h	4934	0644	edit dl rm
m54xxgpt.h	3750	0644	edit dl rm
m54xxpci.h	6276	0644	edit dl rm
m54xxsim.h	3892	0644	edit dl rm
m520xsim.h	7323	0644	edit dl rm
m523xsim.h	7882	0644	edit dl rm
m525xsim.h	10822	0644	edit dl rm
m527xsim.h	13835	0644	edit dl rm
m528xsim.h	9599	0644	edit dl rm
m5206sim.h	6555	0644	edit dl rm
m5272sim.h	6199	0644	edit dl rm
m5307sim.h	7698	0644	edit dl rm
m5407sim.h	6289	0644	edit dl rm
m5441xsim.h	10294	0644	edit dl rm
machdep.h	1331	0644	edit dl rm
machines.h	3209	0644	edit dl rm
machw.h	588	0644	edit dl rm
macintosh.h	2438	0644	edit dl rm
macints.h	3210	0644	edit dl rm
mac_asc.h	520	0644	edit dl rm
mac_baboon.h	999	0644	edit dl rm
mac_iop.h	5499	0644	edit dl rm
mac_oss.h	1873	0644	edit dl rm
mac_psc.h	7427	0644	edit dl rm
mac_via.h	11718	0644	edit dl rm
math-emu.h	6897	0644	edit dl rm
MC68EZ328.h	38650	0644	edit dl rm
MC68VZ328.h	42006	0644	edit dl rm
MC68328.h	38724	0644	edit dl rm
mc146818rtc.h	598	0644	edit dl rm
mcf8390.h	3844	0644	edit dl rm
mcfclk.h	961	0644	edit dl rm
mcfdma.h	6662	0644	edit dl rm
mcfgpio.h	8269	0644	edit dl rm
mcfintc.h	3161	0644	edit dl rm
mcfmmu.h	3761	0644	edit dl rm
mcfpit.h	2278	0644	edit dl rm
mcfqspi.h	1466	0644	edit dl rm
mcfsim.h	1531	0644	edit dl rm
mcfslt.h	1240	0644	edit dl rm
mcftimer.h	2357	0644	edit dl rm
mcfuart.h	7076	0644	edit dl rm
mcfwdebug.h	5106	0644	edit dl rm
mcf_pgalloc.h	2000	0644	edit dl rm
mcf_pgtable.h	8312	0644	edit dl rm
mmu.h	243	0644	edit dl rm
mmu_context.h	7207	0644	edit dl rm
module.h	847	0644	edit dl rm
module.lds.h	91	0644	edit dl rm
motorola_pgalloc.h	2146	0644	edit dl rm
motorola_pgtable.h	7610	0644	edit dl rm
movs.h	1472	0644	edit dl rm
mvme16xhw.h	2216	0644	edit dl rm
mvme147hw.h	2938	0644	edit dl rm
natfeat.h	533	0644	edit dl rm
nettel.h	3023	0644	edit dl rm
nubus.h	1262	0644	edit dl rm
openprom.h	8173	0644	edit dl rm
oplib.h	9768	0644	edit dl rm
page.h	1728	0644	edit dl rm
page_mm.h	3399	0644	edit dl rm
page_no.h	1322	0644	edit dl rm
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parport.h	837	0644	edit dl rm
pci.h	258	0644	edit dl rm
pgalloc.h	444	0644	edit dl rm
pgtable.h	127	0644	edit dl rm
pgtable_mm.h	4931	0644	edit dl rm
pgtable_no.h	1438	0644	edit dl rm
processor.h	4158	0644	edit dl rm
ptrace.h	643	0644	edit dl rm
q40ints.h	749	0644	edit dl rm
q40_master.h	2357	0644	edit dl rm
quicc_simple.h	1830	0644	edit dl rm
raw_io.h	12003	0644	edit dl rm
serial.h	1165	0644	edit dl rm
setup.h	9467	0644	edit dl rm
signal.h	1377	0644	edit dl rm
smp.h	32	0644	edit dl rm
string.h	1717	0644	edit dl rm
sun3-head.h	353	0644	edit dl rm
sun3ints.h	989	0644	edit dl rm
sun3mmu.h	5025	0644	edit dl rm
sun3x.h	868	0644	edit dl rm
sun3xflop.h	5757	0644	edit dl rm
sun3xprom.h	1343	0644	edit dl rm
sun3_pgalloc.h	1267	0644	edit dl rm
sun3_pgtable.h	6583	0644	edit dl rm
switch_to.h	1549	0644	edit dl rm
syscall.h	251	0644	edit dl rm
thread_info.h	2237	0644	edit dl rm
timex.h	974	0644	edit dl rm
tlb.h	135	0644	edit dl rm
tlbflush.h	5989	0644	edit dl rm
traps.h	8615	0644	edit dl rm
uaccess.h	12563	0644	edit dl rm
ucontext.h	570	0644	edit dl rm
unistd.h	993	0644	edit dl rm
user.h	3874	0644	edit dl rm
vga.h	902	0644	edit dl rm
virtconvert.h	834	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
zorro.h	1222	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/m68k/include/asm/m5272sim.h (6199B)

/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************/

/*
 *	m5272sim.h -- ColdFire 5272 System Integration Module support.
 *
 *	(C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
 * 	(C) Copyright 2000, Lineo Inc. (www.lineo.com) 
 */

/****************************************************************************/
#ifndef	m5272sim_h
#define	m5272sim_h
/****************************************************************************/

#define	CPU_NAME		"COLDFIRE(m5272)"
#define	CPU_INSTR_PER_JIFFY	3
#define	MCF_BUSCLK		MCF_CLK

#include <asm/m52xxacr.h>

/*
 *	Define the 5272 SIM register set addresses.
 */
#define	MCFSIM_SCR		(MCF_MBAR + 0x04)	/* SIM Config reg */
#define	MCFSIM_SPR		(MCF_MBAR + 0x06)	/* System Protection */
#define	MCFSIM_PMR		(MCF_MBAR + 0x08)	/* Power Management */
#define	MCFSIM_APMR		(MCF_MBAR + 0x0e)	/* Active Low Power */
#define	MCFSIM_DIR		(MCF_MBAR + 0x10)	/* Device Identity */

#define	MCFSIM_ICR1		(MCF_MBAR + 0x20)	/* Intr Ctrl reg 1 */
#define	MCFSIM_ICR2		(MCF_MBAR + 0x24)	/* Intr Ctrl reg 2 */
#define	MCFSIM_ICR3		(MCF_MBAR + 0x28)	/* Intr Ctrl reg 3 */
#define	MCFSIM_ICR4		(MCF_MBAR + 0x2c)	/* Intr Ctrl reg 4 */

#define	MCFSIM_ISR		(MCF_MBAR + 0x30)	/* Intr Source */
#define	MCFSIM_PITR		(MCF_MBAR + 0x34)	/* Intr Transition */
#define	MCFSIM_PIWR		(MCF_MBAR + 0x38)	/* Intr Wakeup */
#define	MCFSIM_PIVR		(MCF_MBAR + 0x3f)	/* Intr Vector */

#define	MCFSIM_WRRR		(MCF_MBAR + 0x280)	/* Watchdog reference */
#define	MCFSIM_WIRR		(MCF_MBAR + 0x284)	/* Watchdog interrupt */
#define	MCFSIM_WCR		(MCF_MBAR + 0x288)	/* Watchdog counter */
#define	MCFSIM_WER		(MCF_MBAR + 0x28c)	/* Watchdog event */

#define	MCFSIM_CSBR0		(MCF_MBAR + 0x40)	/* CS0 Base Address */
#define	MCFSIM_CSOR0		(MCF_MBAR + 0x44)	/* CS0 Option */
#define	MCFSIM_CSBR1		(MCF_MBAR + 0x48)	/* CS1 Base Address */
#define	MCFSIM_CSOR1		(MCF_MBAR + 0x4c)	/* CS1 Option */
#define	MCFSIM_CSBR2		(MCF_MBAR + 0x50)	/* CS2 Base Address */
#define	MCFSIM_CSOR2		(MCF_MBAR + 0x54)	/* CS2 Option */
#define	MCFSIM_CSBR3		(MCF_MBAR + 0x58)	/* CS3 Base Address */
#define	MCFSIM_CSOR3		(MCF_MBAR + 0x5c)	/* CS3 Option */
#define	MCFSIM_CSBR4		(MCF_MBAR + 0x60)	/* CS4 Base Address */
#define	MCFSIM_CSOR4		(MCF_MBAR + 0x64)	/* CS4 Option */
#define	MCFSIM_CSBR5		(MCF_MBAR + 0x68)	/* CS5 Base Address */
#define	MCFSIM_CSOR5		(MCF_MBAR + 0x6c)	/* CS5 Option */
#define	MCFSIM_CSBR6		(MCF_MBAR + 0x70)	/* CS6 Base Address */
#define	MCFSIM_CSOR6		(MCF_MBAR + 0x74)	/* CS6 Option */
#define	MCFSIM_CSBR7		(MCF_MBAR + 0x78)	/* CS7 Base Address */
#define	MCFSIM_CSOR7		(MCF_MBAR + 0x7c)	/* CS7 Option */

#define	MCFSIM_SDCR		(MCF_MBAR + 0x180)	/* SDRAM Config */
#define	MCFSIM_SDTR		(MCF_MBAR + 0x184)	/* SDRAM Timing */
#define	MCFSIM_DCAR0		(MCF_MBAR + 0x4c)	/* DRAM 0 Address */
#define	MCFSIM_DCMR0		(MCF_MBAR + 0x50)	/* DRAM 0 Mask */
#define	MCFSIM_DCCR0		(MCF_MBAR + 0x57)	/* DRAM 0 Control */
#define	MCFSIM_DCAR1		(MCF_MBAR + 0x58)	/* DRAM 1 Address */
#define	MCFSIM_DCMR1		(MCF_MBAR + 0x5c)	/* DRAM 1 Mask reg */
#define	MCFSIM_DCCR1		(MCF_MBAR + 0x63)	/* DRAM 1 Control */

#define	MCFUART_BASE0		(MCF_MBAR + 0x100) /* Base address UART0 */
#define	MCFUART_BASE1		(MCF_MBAR + 0x140) /* Base address UART1 */

#define	MCFSIM_PACNT		(MCF_MBAR + 0x80) /* Port A Control (r/w) */
#define	MCFSIM_PADDR		(MCF_MBAR + 0x84) /* Port A Direction (r/w) */
#define	MCFSIM_PADAT		(MCF_MBAR + 0x86) /* Port A Data (r/w) */
#define	MCFSIM_PBCNT		(MCF_MBAR + 0x88) /* Port B Control (r/w) */
#define	MCFSIM_PBDDR		(MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
#define	MCFSIM_PBDAT		(MCF_MBAR + 0x8e) /* Port B Data (r/w) */
#define	MCFSIM_PCDDR		(MCF_MBAR + 0x94) /* Port C Direction (r/w) */
#define	MCFSIM_PCDAT		(MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define	MCFSIM_PDCNT		(MCF_MBAR + 0x98) /* Port D Control (r/w) */

#define	MCFDMA_BASE0		(MCF_MBAR + 0xe0) /* Base address DMA 0 */

#define	MCFTIMER_BASE1		(MCF_MBAR + 0x200) /* Base address TIMER1 */
#define	MCFTIMER_BASE2		(MCF_MBAR + 0x220) /* Base address TIMER2 */
#define	MCFTIMER_BASE3		(MCF_MBAR + 0x240) /* Base address TIMER4 */
#define	MCFTIMER_BASE4		(MCF_MBAR + 0x260) /* Base address TIMER3 */

#define	MCFFEC_BASE0		(MCF_MBAR + 0x840) /* Base FEC ethernet */
#define	MCFFEC_SIZE0		0x1d0

/*
 *	Define system peripheral IRQ usage.
 */
#define	MCFINT_VECBASE		64		/* Base of interrupts */
#define	MCF_IRQ_SPURIOUS	64		/* User Spurious */
#define	MCF_IRQ_EINT1		65		/* External Interrupt 1 */
#define	MCF_IRQ_EINT2		66		/* External Interrupt 2 */
#define	MCF_IRQ_EINT3		67		/* External Interrupt 3 */
#define	MCF_IRQ_EINT4		68		/* External Interrupt 4 */
#define	MCF_IRQ_TIMER1		69		/* Timer 1 */
#define	MCF_IRQ_TIMER2		70		/* Timer 2 */
#define	MCF_IRQ_TIMER3		71		/* Timer 3 */
#define	MCF_IRQ_TIMER4		72		/* Timer 4 */
#define	MCF_IRQ_UART0		73		/* UART 0 */
#define	MCF_IRQ_UART1		74		/* UART 1 */
#define	MCF_IRQ_PLIP		75		/* PLIC 2Khz Periodic */
#define	MCF_IRQ_PLIA		76		/* PLIC Asynchronous */
#define	MCF_IRQ_USB0		77		/* USB Endpoint 0 */
#define	MCF_IRQ_USB1		78		/* USB Endpoint 1 */
#define	MCF_IRQ_USB2		79		/* USB Endpoint 2 */
#define	MCF_IRQ_USB3		80		/* USB Endpoint 3 */
#define	MCF_IRQ_USB4		81		/* USB Endpoint 4 */
#define	MCF_IRQ_USB5		82		/* USB Endpoint 5 */
#define	MCF_IRQ_USB6		83		/* USB Endpoint 6 */
#define	MCF_IRQ_USB7		84		/* USB Endpoint 7 */
#define	MCF_IRQ_DMA		85		/* DMA Controller */
#define	MCF_IRQ_FECRX0		86		/* Ethernet Receiver */
#define	MCF_IRQ_FECTX0		87		/* Ethernet Transmitter */
#define	MCF_IRQ_FECENTC0	88		/* Ethernet Non-Time Critical */
#define	MCF_IRQ_QSPI		89		/* Queued Serial Interface */
#define	MCF_IRQ_EINT5		90		/* External Interrupt 5 */
#define	MCF_IRQ_EINT6		91		/* External Interrupt 6 */
#define	MCF_IRQ_SWTO		92		/* Software Watchdog */
#define	MCFINT_VECMAX		95		/* Maxmum interrupt */

#define	MCF_IRQ_TIMER		MCF_IRQ_TIMER1
#define	MCF_IRQ_PROFILER	MCF_IRQ_TIMER2

/*
 * Generic GPIO support
 */
#define MCFGPIO_PIN_MAX		48
#define MCFGPIO_IRQ_MAX		-1
#define MCFGPIO_IRQ_VECBASE	-1

/****************************************************************************/
#endif	/* m5272sim_h */

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