FM / asm

/usr/src/linux-headers-5.15.0-181/arch/m68k/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/m68k/include/asm

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adb_iop.h	1188	0644	edit dl rm
amigahw.h	10737	0644	edit dl rm
amigaints.h	3583	0644	edit dl rm
amigayle.h	3271	0644	edit dl rm
amipcmcia.h	2568	0644	edit dl rm
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asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	211	0644	edit dl rm
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cacheflush_no.h	1884	0644	edit dl rm
checksum.h	3497	0644	edit dl rm
cmpxchg.h	3189	0644	edit dl rm
coldfire.h	1653	0644	edit dl rm
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export.h	53	0644	edit dl rm
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gpio.h	2294	0644	edit dl rm
hash.h	2115	0644	edit dl rm
hp300hw.h	186	0644	edit dl rm
hwtest.h	467	0644	edit dl rm
ide.h	1708	0644	edit dl rm
idprom.h	725	0644	edit dl rm
intersil.h	1134	0644	edit dl rm
io.h	244	0644	edit dl rm
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irq.h	2634	0644	edit dl rm
irqflags.h	1652	0644	edit dl rm
Kbuild	165	0644	edit dl rm
kexec.h	732	0644	edit dl rm
kmap.h	1754	0644	edit dl rm
linkage.h	1583	0644	edit dl rm
m52xxacr.h	3660	0644	edit dl rm
m53xxacr.h	3683	0644	edit dl rm
m53xxsim.h	55262	0644	edit dl rm
m54xxacr.h	4934	0644	edit dl rm
m54xxgpt.h	3750	0644	edit dl rm
m54xxpci.h	6276	0644	edit dl rm
m54xxsim.h	3892	0644	edit dl rm
m520xsim.h	7323	0644	edit dl rm
m523xsim.h	7882	0644	edit dl rm
m525xsim.h	10822	0644	edit dl rm
m527xsim.h	13835	0644	edit dl rm
m528xsim.h	9599	0644	edit dl rm
m5206sim.h	6555	0644	edit dl rm
m5272sim.h	6199	0644	edit dl rm
m5307sim.h	7698	0644	edit dl rm
m5407sim.h	6289	0644	edit dl rm
m5441xsim.h	10294	0644	edit dl rm
machdep.h	1331	0644	edit dl rm
machines.h	3209	0644	edit dl rm
machw.h	588	0644	edit dl rm
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macints.h	3210	0644	edit dl rm
mac_asc.h	520	0644	edit dl rm
mac_baboon.h	999	0644	edit dl rm
mac_iop.h	5499	0644	edit dl rm
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mac_psc.h	7427	0644	edit dl rm
mac_via.h	11718	0644	edit dl rm
math-emu.h	6897	0644	edit dl rm
MC68EZ328.h	38650	0644	edit dl rm
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MC68328.h	38724	0644	edit dl rm
mc146818rtc.h	598	0644	edit dl rm
mcf8390.h	3844	0644	edit dl rm
mcfclk.h	961	0644	edit dl rm
mcfdma.h	6662	0644	edit dl rm
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mcfintc.h	3161	0644	edit dl rm
mcfmmu.h	3761	0644	edit dl rm
mcfpit.h	2278	0644	edit dl rm
mcfqspi.h	1466	0644	edit dl rm
mcfsim.h	1531	0644	edit dl rm
mcfslt.h	1240	0644	edit dl rm
mcftimer.h	2357	0644	edit dl rm
mcfuart.h	7076	0644	edit dl rm
mcfwdebug.h	5106	0644	edit dl rm
mcf_pgalloc.h	2000	0644	edit dl rm
mcf_pgtable.h	8312	0644	edit dl rm
mmu.h	243	0644	edit dl rm
mmu_context.h	7207	0644	edit dl rm
module.h	847	0644	edit dl rm
module.lds.h	91	0644	edit dl rm
motorola_pgalloc.h	2146	0644	edit dl rm
motorola_pgtable.h	7610	0644	edit dl rm
movs.h	1472	0644	edit dl rm
mvme16xhw.h	2216	0644	edit dl rm
mvme147hw.h	2938	0644	edit dl rm
natfeat.h	533	0644	edit dl rm
nettel.h	3023	0644	edit dl rm
nubus.h	1262	0644	edit dl rm
openprom.h	8173	0644	edit dl rm
oplib.h	9768	0644	edit dl rm
page.h	1728	0644	edit dl rm
page_mm.h	3399	0644	edit dl rm
page_no.h	1322	0644	edit dl rm
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parport.h	837	0644	edit dl rm
pci.h	258	0644	edit dl rm
pgalloc.h	444	0644	edit dl rm
pgtable.h	127	0644	edit dl rm
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pgtable_no.h	1438	0644	edit dl rm
processor.h	4158	0644	edit dl rm
ptrace.h	643	0644	edit dl rm
q40ints.h	749	0644	edit dl rm
q40_master.h	2357	0644	edit dl rm
quicc_simple.h	1830	0644	edit dl rm
raw_io.h	12003	0644	edit dl rm
serial.h	1165	0644	edit dl rm
setup.h	9467	0644	edit dl rm
signal.h	1377	0644	edit dl rm
smp.h	32	0644	edit dl rm
string.h	1717	0644	edit dl rm
sun3-head.h	353	0644	edit dl rm
sun3ints.h	989	0644	edit dl rm
sun3mmu.h	5025	0644	edit dl rm
sun3x.h	868	0644	edit dl rm
sun3xflop.h	5757	0644	edit dl rm
sun3xprom.h	1343	0644	edit dl rm
sun3_pgalloc.h	1267	0644	edit dl rm
sun3_pgtable.h	6583	0644	edit dl rm
switch_to.h	1549	0644	edit dl rm
syscall.h	251	0644	edit dl rm
thread_info.h	2237	0644	edit dl rm
timex.h	974	0644	edit dl rm
tlb.h	135	0644	edit dl rm
tlbflush.h	5989	0644	edit dl rm
traps.h	8615	0644	edit dl rm
uaccess.h	12563	0644	edit dl rm
ucontext.h	570	0644	edit dl rm
unistd.h	993	0644	edit dl rm
user.h	3874	0644	edit dl rm
vga.h	902	0644	edit dl rm
virtconvert.h	834	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
zorro.h	1222	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/m68k/include/asm/m5307sim.h (7698B)

/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************/

/*
 *	m5307sim.h -- ColdFire 5307 System Integration Module support.
 *
 *	(C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
 *	(C) Copyright 1999,  Lineo (www.lineo.com)
 *
 *      Modified by David W. Miller for the MCF5307 Eval Board.
 */

/****************************************************************************/
#ifndef	m5307sim_h
#define	m5307sim_h
/****************************************************************************/

#define	CPU_NAME		"COLDFIRE(m5307)"
#define	CPU_INSTR_PER_JIFFY	3
#define	MCF_BUSCLK		(MCF_CLK / 2)

#include <asm/m53xxacr.h>

/*
 *	Define the 5307 SIM register set addresses.
 */
#define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status reg */
#define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
#define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
#define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
#define	MCFSIM_IRQPAR		(MCF_MBAR + 0x06)	/* Itr Assignment */
#define	MCFSIM_PLLCR		(MCF_MBAR + 0x08)	/* PLL Ctrl Reg */
#define	MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
#define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pend */
#define	MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
#define	MCFSIM_AVR		(MCF_MBAR + 0x4b)	/* Autovector Ctrl */
#define	MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
#define	MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
#define	MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
#define	MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
#define	MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
#define	MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
#define	MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
#define	MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
#define	MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
#define	MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
#define	MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
#define	MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */

#define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
#define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
#define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
#define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
#define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
#define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */

#ifdef CONFIG_OLDMASK
#define MCFSIM_CSBAR		(MCF_MBAR + 0x98)	/* CS Base Address */
#define MCFSIM_CSBAMR		(MCF_MBAR + 0x9c)	/* CS Base Mask */
#define MCFSIM_CSMR2		(MCF_MBAR + 0x9e)	/* CS 2 Mask reg */
#define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
#define MCFSIM_CSMR3		(MCF_MBAR + 0xaa)	/* CS 3 Mask reg */
#define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
#define MCFSIM_CSMR4		(MCF_MBAR + 0xb6)	/* CS 4 Mask reg */
#define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
#define MCFSIM_CSMR5		(MCF_MBAR + 0xc2)	/* CS 5 Mask reg */
#define MCFSIM_CSCR5		(MCF_MBAR + 0xc6)	/* CS 5 Control reg */
#define MCFSIM_CSMR6		(MCF_MBAR + 0xce)	/* CS 6 Mask reg */
#define MCFSIM_CSCR6		(MCF_MBAR + 0xd2)	/* CS 6 Control reg */
#define MCFSIM_CSMR7		(MCF_MBAR + 0xda)	/* CS 7 Mask reg */
#define MCFSIM_CSCR7		(MCF_MBAR + 0xde)	/* CS 7 Control reg */
#else
#define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
#define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
#define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
#define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
#define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
#define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
#define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
#define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
#define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
#define MCFSIM_CSAR5		(MCF_MBAR + 0xbc)	/* CS 5 Address reg */
#define MCFSIM_CSMR5		(MCF_MBAR + 0xc0)	/* CS 5 Mask reg */
#define MCFSIM_CSCR5		(MCF_MBAR + 0xc6)	/* CS 5 Control reg */
#define MCFSIM_CSAR6		(MCF_MBAR + 0xc8)	/* CS 6 Address reg */
#define MCFSIM_CSMR6		(MCF_MBAR + 0xcc)	/* CS 6 Mask reg */
#define MCFSIM_CSCR6		(MCF_MBAR + 0xd2)	/* CS 6 Control reg */
#define MCFSIM_CSAR7		(MCF_MBAR + 0xd4)	/* CS 7 Address reg */
#define MCFSIM_CSMR7		(MCF_MBAR + 0xd8)	/* CS 7 Mask reg */
#define MCFSIM_CSCR7		(MCF_MBAR + 0xde)	/* CS 7 Control reg */
#endif /* CONFIG_OLDMASK */

#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM Addr/Ctrl 0 */
#define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM Mask 0 */
#define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM Addr/Ctrl 1 */
#define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM Mask 1 */

/*
 *  Timer module.
 */
#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */

#define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
#define	MCFSIM_PADAT		(MCF_MBAR + 0x248)

/*
 *  DMA unit base addresses.
 */
#define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
#define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
#define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
#define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */

/*
 *  UART module.
 */
#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE0		(MCF_MBAR + 0x200)	/* Base address UART0 */
#define MCFUART_BASE1		(MCF_MBAR + 0x1c0)	/* Base address UART1 */
#else
#define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
#define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */
#endif

/*
 * Generic GPIO support
 */
#define MCFGPIO_PIN_MAX		16
#define MCFGPIO_IRQ_MAX		-1
#define MCFGPIO_IRQ_VECBASE	-1

/* Definition offset address for CS2-7  -- old mask 5307 */

#define	MCF5307_CS2		(0x400000)
#define	MCF5307_CS3		(0x600000)
#define	MCF5307_CS4		(0x800000)
#define	MCF5307_CS5		(0xA00000)
#define	MCF5307_CS6		(0xC00000)
#define	MCF5307_CS7		(0xE00000)

/*
 *	Some symbol defines for the above...
 */
#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
#define	MCFSIM_I2CICR		MCFSIM_ICR3	/* I2C ICR */
#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
#define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
#define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
#define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
#define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */

/*
 *	Some symbol defines for the Parallel Port Pin Assignment Register
 */
#define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
                                                /* Clear to select par I/O */
#define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
                                                /* Clear to select par I/O */

/*
 *       Defines for the IRQPAR Register
 */
#define IRQ5_LEVEL4		0x80
#define IRQ3_LEVEL6		0x40
#define IRQ1_LEVEL2		0x20

/*
 *	Define system peripheral IRQ usage.
 */
#define	MCF_IRQ_I2C0		29		/* I2C, Level 5 */
#define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */
#define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */
#define	MCF_IRQ_UART0		73		/* UART0 */
#define	MCF_IRQ_UART1		74		/* UART1 */

/*
 * I2C module
 */
#define	MCFI2C_BASE0		(MCF_MBAR + 0x280)
#define	MCFI2C_SIZE0		0x40

/****************************************************************************/
#endif	/* m5307sim_h */

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