FM / asm

/usr/src/linux-headers-5.15.0-181/arch/mips/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/mips/include/asm

Name	Size	Mode	Actions
dec/	-	0755	rm
fw/	-	0755	rm
ip32/	-	0755	rm
mach-ar7/	-	0755	rm
mach-ath25/	-	0755	rm
mach-ath79/	-	0755	rm
mach-au1x00/	-	0755	rm
mach-bcm47xx/	-	0755	rm
mach-bcm63xx/	-	0755	rm
mach-bmips/	-	0755	rm
mach-cavium-octeon/	-	0755	rm
mach-cobalt/	-	0755	rm
mach-db1x00/	-	0755	rm
mach-dec/	-	0755	rm
mach-generic/	-	0755	rm
mach-ingenic/	-	0755	rm
mach-ip22/	-	0755	rm
mach-ip27/	-	0755	rm
mach-ip28/	-	0755	rm
mach-ip30/	-	0755	rm
mach-ip32/	-	0755	rm
mach-jazz/	-	0755	rm
mach-lantiq/	-	0755	rm
mach-loongson2ef/	-	0755	rm
mach-loongson32/	-	0755	rm
mach-loongson64/	-	0755	rm
mach-malta/	-	0755	rm
mach-n64/	-	0755	rm
mach-netlogic/	-	0755	rm
mach-pic32/	-	0755	rm
mach-ralink/	-	0755	rm
mach-rc32434/	-	0755	rm
mach-rm/	-	0755	rm
mach-sibyte/	-	0755	rm
mach-tx39xx/	-	0755	rm
mach-tx49xx/	-	0755	rm
mach-vr41xx/	-	0755	rm
mips-boards/	-	0755	rm
netlogic/	-	0755	rm
octeon/	-	0755	rm
pci/	-	0755	rm
sgi/	-	0755	rm
sibyte/	-	0755	rm
sn/	-	0755	rm
txx9/	-	0755	rm
vdso/	-	0755	rm
vr41xx/	-	0755	rm
xtalk/	-	0755	rm
abi.h	853	0644	edit dl rm
addrspace.h	4039	0644	edit dl rm
amon.h	409	0644	edit dl rm
arch_hweight.h	792	0644	edit dl rm
asm-eva.h	7343	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	228	0644	edit dl rm
asm.h	6688	0644	edit dl rm
asmmacro-32.h	2529	0644	edit dl rm
asmmacro-64.h	1254	0644	edit dl rm
asmmacro.h	14639	0644	edit dl rm
atomic.h	8299	0644	edit dl rm
barrier.h	3507	0644	edit dl rm
bcache.h	2086	0644	edit dl rm
bitops.h	10914	0644	edit dl rm
bitrev.h	608	0644	edit dl rm
bmips-spaces.h	268	0644	edit dl rm
bmips.h	3097	0644	edit dl rm
bootinfo.h	4928	0644	edit dl rm
branch.h	2503	0644	edit dl rm
break.h	787	0644	edit dl rm
bug.h	759	0644	edit dl rm
bugs.h	640	0644	edit dl rm
cache.h	527	0644	edit dl rm
cacheflush.h	4863	0644	edit dl rm
cacheops.h	3801	0644	edit dl rm
cdmm.h	3761	0644	edit dl rm
cevt-r4k.h	823	0644	edit dl rm
checksum.h	5743	0644	edit dl rm
clocksource.h	273	0644	edit dl rm
cmp.h	492	0644	edit dl rm
cmpxchg.h	8880	0644	edit dl rm
compat-signal.h	640	0644	edit dl rm
compat.h	3866	0644	edit dl rm
compiler.h	2669	0644	edit dl rm
cop2.h	1812	0644	edit dl rm
cpu-features.h	22752	0644	edit dl rm
cpu-info.h	6303	0644	edit dl rm
cpu-type.h	4256	0644	edit dl rm
cpu.h	16955	0644	edit dl rm
cpufeature.h	510	0644	edit dl rm
debug.h	447	0644	edit dl rm
delay.h	841	0644	edit dl rm
div64.h	2223	0644	edit dl rm
dma-direct.h	255	0644	edit dl rm
dma-mapping.h	365	0644	edit dl rm
dma.h	10161	0644	edit dl rm
dmi.h	547	0644	edit dl rm
ds1287.h	333	0644	edit dl rm
dsemul.h	3595	0644	edit dl rm
dsp.h	1747	0644	edit dl rm
edac.h	839	0644	edit dl rm
elf.h	15559	0644	edit dl rm
elfcore-compat.h	841	0644	edit dl rm
errno.h	429	0644	edit dl rm
eva.h	796	0644	edit dl rm
exec.h	579	0644	edit dl rm
extable.h	241	0644	edit dl rm
fb.h	372	0644	edit dl rm
fixmap.h	2219	0644	edit dl rm
floppy.h	1609	0644	edit dl rm
fpregdef.h	2726	0644	edit dl rm
fpu.h	7332	0644	edit dl rm
fpu_emulator.h	4844	0644	edit dl rm
ftrace.h	2659	0644	edit dl rm
futex.h	5241	0644	edit dl rm
ginvt.h	1056	0644	edit dl rm
gio_device.h	1411	0644	edit dl rm
gt64120.h	19218	0644	edit dl rm
hardirq.h	544	0644	edit dl rm
hazards.h	8673	0644	edit dl rm
highmem.h	1741	0644	edit dl rm
hpet.h	1974	0644	edit dl rm
hugetlb.h	2165	0644	edit dl rm
hw_irq.h	475	0644	edit dl rm
i8259.h	2440	0644	edit dl rm
ide.h	330	0644	edit dl rm
idle.h	727	0644	edit dl rm
inst.h	2398	0644	edit dl rm
io.h	17334	0644	edit dl rm
irq.h	2408	0644	edit dl rm
irqflags.h	4206	0644	edit dl rm
irq_cpu.h	427	0644	edit dl rm
irq_gt641xx.h	2074	0644	edit dl rm
irq_regs.h	540	0644	edit dl rm
isa-rev.h	556	0644	edit dl rm
isadep.h	603	0644	edit dl rm
jazz.h	8192	0644	edit dl rm
jazzdma.h	2826	0644	edit dl rm
jump_label.h	1571	0644	edit dl rm
Kbuild	414	0644	edit dl rm
kdebug.h	303	0644	edit dl rm
kexec.h	1490	0644	edit dl rm
kgdb.h	1222	0644	edit dl rm
kprobes.h	1727	0644	edit dl rm
kvm_host.h	30488	0644	edit dl rm
kvm_types.h	184	0644	edit dl rm
linkage.h	306	0644	edit dl rm
llsc.h	923	0644	edit dl rm
local.h	5473	0644	edit dl rm
maar.h	4270	0644	edit dl rm
machine.h	2795	0644	edit dl rm
mc146818-time.h	3779	0644	edit dl rm
mc146818rtc.h	450	0644	edit dl rm
mips-cm.h	16857	0644	edit dl rm
mips-cpc.h	5766	0644	edit dl rm
mips-cps.h	6494	0644	edit dl rm
mips-gic.h	12387	0644	edit dl rm
mips-r2-to-r6-emul.h	2095	0644	edit dl rm
mipsmtregs.h	11171	0644	edit dl rm
mipsprom.h	2146	0644	edit dl rm
mipsregs.h	96792	0644	edit dl rm
mips_mt.h	707	0644	edit dl rm
mmiowb.h	197	0644	edit dl rm
mmu.h	555	0644	edit dl rm
mmu_context.h	6205	0644	edit dl rm
mmzone.h	427	0644	edit dl rm
module.h	2388	0644	edit dl rm
msa.h	7525	0644	edit dl rm
msc01_ic.h	6709	0644	edit dl rm
paccess.h	3140	0644	edit dl rm
page.h	7610	0644	edit dl rm
pci.h	3902	0644	edit dl rm
perf_event.h	336	0644	edit dl rm
pgalloc.h	2571	0644	edit dl rm
pgtable-32.h	8149	0644	edit dl rm
pgtable-64.h	9709	0644	edit dl rm
pgtable-bits.h	7852	0644	edit dl rm
pgtable.h	18529	0644	edit dl rm
pm-cps.h	1515	0644	edit dl rm
pm.h	3871	0644	edit dl rm
prefetch.h	2148	0644	edit dl rm
processor.h	11321	0644	edit dl rm
prom.h	696	0644	edit dl rm
ptrace.h	5582	0644	edit dl rm
r4k-timer.h	604	0644	edit dl rm
r4kcache.h	11373	0644	edit dl rm
reboot.h	440	0644	edit dl rm
reg.h	26	0644	edit dl rm
regdef.h	2693	0644	edit dl rm
rtlx.h	2148	0644	edit dl rm
seccomp.h	810	0644	edit dl rm
setup.h	941	0644	edit dl rm
sgialib.h	1743	0644	edit dl rm
sgiarcs.h	14022	0644	edit dl rm
shmparam.h	352	0644	edit dl rm
sigcontext.h	1060	0644	edit dl rm
signal.h	1042	0644	edit dl rm
sim.h	2070	0644	edit dl rm
smp-cps.h	998	0644	edit dl rm
smp-ops.h	2476	0644	edit dl rm
smp.h	3696	0644	edit dl rm
sni.h	7495	0644	edit dl rm
socket.h	1377	0644	edit dl rm
sparsemem.h	486	0644	edit dl rm
spinlock.h	822	0644	edit dl rm
spinlock_types.h	188	0644	edit dl rm
spram.h	261	0644	edit dl rm
stackframe.h	11157	0644	edit dl rm
stackprotector.h	1177	0644	edit dl rm
stacktrace.h	2199	0644	edit dl rm
string.h	692	0644	edit dl rm
switch_to.h	4455	0644	edit dl rm
sync.h	7823	0644	edit dl rm
syscall.h	3703	0644	edit dl rm
termios.h	2933	0644	edit dl rm
thread_info.h	6640	0644	edit dl rm
time.h	1617	0644	edit dl rm
timex.h	2937	0644	edit dl rm
tlb.h	613	0644	edit dl rm
tlbdebug.h	403	0644	edit dl rm
tlbex.h	977	0644	edit dl rm
tlbflush.h	1683	0644	edit dl rm
tlbmisc.h	320	0644	edit dl rm
topology.h	619	0644	edit dl rm
traps.h	1229	0644	edit dl rm
txx9irq.h	743	0644	edit dl rm
txx9pio.h	592	0644	edit dl rm
txx9tmr.h	1625	0644	edit dl rm
types.h	459	0644	edit dl rm
uaccess.h	16450	0644	edit dl rm
uasm.h	9578	0644	edit dl rm
unaligned-emul.h	26856	0644	edit dl rm
unistd.h	1860	0644	edit dl rm
unroll.h	2860	0644	edit dl rm
uprobes.h	1141	0644	edit dl rm
vdso.h	1469	0644	edit dl rm
vermagic.h	2372	0644	edit dl rm
vga.h	1291	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
vpe.h	2843	0644	edit dl rm
war.h	2282	0644	edit dl rm
watch.h	827	0644	edit dl rm
wbflush.h	694	0644	edit dl rm
yamon-dt.h	1717	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/mips/include/asm/asmmacro.h (14639B)

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Ralf Baechle
 */
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H

#include <asm/hazards.h>
#include <asm/asm-offsets.h>
#include <asm/msa.h>

#ifdef CONFIG_32BIT
#include <asm/asmmacro-32.h>
#endif
#ifdef CONFIG_64BIT
#include <asm/asmmacro-64.h>
#endif

/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
#undef fp

/*
 * Helper macros for generating raw instruction encodings.
 */
#ifdef CONFIG_CPU_MICROMIPS
	.macro	insn32_if_mm enc
	.insn
	.hword ((\enc) >> 16)
	.hword ((\enc) & 0xffff)
	.endm

.macro	insn_if_mips enc
	.endm
#else
	.macro	insn32_if_mm enc
	.endm

.macro	insn_if_mips enc
	.insn
	.word (\enc)
	.endm
#endif

#ifdef CONFIG_CPU_HAS_DIEI
	.macro	local_irq_enable reg=t0
	ei
	irq_enable_hazard
	.endm

.macro	local_irq_disable reg=t0
	di
	irq_disable_hazard
	.endm
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
	.macro	local_irq_enable reg=t0
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_enable_hazard
	.endm

.macro	local_irq_disable reg=t0
#ifdef CONFIG_PREEMPTION
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, 1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	xori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_disable_hazard
#ifdef CONFIG_PREEMPTION
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, -1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	.endm
#endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */

.macro	fpu_save_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	cfc1	\tmp, fcr31
	sdc1	$f0,  THREAD_FPR0(\thread)
	sdc1	$f2,  THREAD_FPR2(\thread)
	sdc1	$f4,  THREAD_FPR4(\thread)
	sdc1	$f6,  THREAD_FPR6(\thread)
	sdc1	$f8,  THREAD_FPR8(\thread)
	sdc1	$f10, THREAD_FPR10(\thread)
	sdc1	$f12, THREAD_FPR12(\thread)
	sdc1	$f14, THREAD_FPR14(\thread)
	sdc1	$f16, THREAD_FPR16(\thread)
	sdc1	$f18, THREAD_FPR18(\thread)
	sdc1	$f20, THREAD_FPR20(\thread)
	sdc1	$f22, THREAD_FPR22(\thread)
	sdc1	$f24, THREAD_FPR24(\thread)
	sdc1	$f26, THREAD_FPR26(\thread)
	sdc1	$f28, THREAD_FPR28(\thread)
	sdc1	$f30, THREAD_FPR30(\thread)
	sw	\tmp, THREAD_FCR31(\thread)
	.set	pop
	.endm

.macro	fpu_save_16odd thread
	.set	push
	.set	mips64r2
	.set	fp=64
	SET_HARDFLOAT
	sdc1	$f1,  THREAD_FPR1(\thread)
	sdc1	$f3,  THREAD_FPR3(\thread)
	sdc1	$f5,  THREAD_FPR5(\thread)
	sdc1	$f7,  THREAD_FPR7(\thread)
	sdc1	$f9,  THREAD_FPR9(\thread)
	sdc1	$f11, THREAD_FPR11(\thread)
	sdc1	$f13, THREAD_FPR13(\thread)
	sdc1	$f15, THREAD_FPR15(\thread)
	sdc1	$f17, THREAD_FPR17(\thread)
	sdc1	$f19, THREAD_FPR19(\thread)
	sdc1	$f21, THREAD_FPR21(\thread)
	sdc1	$f23, THREAD_FPR23(\thread)
	sdc1	$f25, THREAD_FPR25(\thread)
	sdc1	$f27, THREAD_FPR27(\thread)
	sdc1	$f29, THREAD_FPR29(\thread)
	sdc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

.macro	fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f
	fpu_save_16odd \thread
10:
#endif
	fpu_save_16even \thread \tmp
	.endm

.macro	fpu_restore_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	lw	\tmp, THREAD_FCR31(\thread)
	ldc1	$f0,  THREAD_FPR0(\thread)
	ldc1	$f2,  THREAD_FPR2(\thread)
	ldc1	$f4,  THREAD_FPR4(\thread)
	ldc1	$f6,  THREAD_FPR6(\thread)
	ldc1	$f8,  THREAD_FPR8(\thread)
	ldc1	$f10, THREAD_FPR10(\thread)
	ldc1	$f12, THREAD_FPR12(\thread)
	ldc1	$f14, THREAD_FPR14(\thread)
	ldc1	$f16, THREAD_FPR16(\thread)
	ldc1	$f18, THREAD_FPR18(\thread)
	ldc1	$f20, THREAD_FPR20(\thread)
	ldc1	$f22, THREAD_FPR22(\thread)
	ldc1	$f24, THREAD_FPR24(\thread)
	ldc1	$f26, THREAD_FPR26(\thread)
	ldc1	$f28, THREAD_FPR28(\thread)
	ldc1	$f30, THREAD_FPR30(\thread)
	ctc1	\tmp, fcr31
	.set	pop
	.endm

.macro	fpu_restore_16odd thread
	.set	push
	.set	mips64r2
	.set	fp=64
	SET_HARDFLOAT
	ldc1	$f1,  THREAD_FPR1(\thread)
	ldc1	$f3,  THREAD_FPR3(\thread)
	ldc1	$f5,  THREAD_FPR5(\thread)
	ldc1	$f7,  THREAD_FPR7(\thread)
	ldc1	$f9,  THREAD_FPR9(\thread)
	ldc1	$f11, THREAD_FPR11(\thread)
	ldc1	$f13, THREAD_FPR13(\thread)
	ldc1	$f15, THREAD_FPR15(\thread)
	ldc1	$f17, THREAD_FPR17(\thread)
	ldc1	$f19, THREAD_FPR19(\thread)
	ldc1	$f21, THREAD_FPR21(\thread)
	ldc1	$f23, THREAD_FPR23(\thread)
	ldc1	$f25, THREAD_FPR25(\thread)
	ldc1	$f27, THREAD_FPR27(\thread)
	ldc1	$f29, THREAD_FPR29(\thread)
	ldc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

.macro	fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f				# 16 register mode?

fpu_restore_16odd \thread
10:
#endif
	fpu_restore_16even \thread \tmp
	.endm

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
    defined(CONFIG_CPU_MIPSR6)
	.macro	_EXT	rd, rs, p, s
	ext	\rd, \rs, \p, \s
	.endm
#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
	.macro	_EXT	rd, rs, p, s
	srl	\rd, \rs, \p
	andi	\rd, \rd, (1 << \s) - 1
	.endm
#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */

/*
 * Temporary until all gas have MT ASE support
 */
	.macro	DMT	reg=0
	.word	0x41600bc1 | (\reg << 16)
	.endm

.macro	EMT	reg=0
	.word	0x41600be1 | (\reg << 16)
	.endm

.macro	DVPE	reg=0
	.word	0x41600001 | (\reg << 16)
	.endm

.macro	EVPE	reg=0
	.word	0x41600021 | (\reg << 16)
	.endm

.macro	MFTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

.macro	MTTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

#ifdef TOOLCHAIN_SUPPORTS_MSA
	.macro	_cfcmsa	rd, cs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	cfcmsa	\rd, $\cs
	.set	pop
	.endm

.macro	_ctcmsa	cd, rs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ctcmsa	$\cd, \rs
	.set	pop
	.endm

.macro	ld_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.b	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	ld_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.h	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	ld_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.w	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	ld_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.d	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	st_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.b	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	st_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.h	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	st_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.w	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	st_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.d	$w\wd, \off(\base)
	.set	pop
	.endm

.macro	copy_s_w	ws, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	copy_s.w $1, $w\ws[\n]
	.set	pop
	.endm

.macro	copy_s_d	ws, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	copy_s.d $1, $w\ws[\n]
	.set	pop
	.endm

.macro	insert_w	wd, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	insert.w $w\wd[\n], $1
	.set	pop
	.endm

.macro	insert_d	wd, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	insert.d $w\wd[\n], $1
	.set	pop
	.endm
#else

/*
	 * Temporary until all toolchains in use include MSA support.
	 */
	.macro	_cfcmsa	rd, cs
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x787e0059 | (\cs << 11)
	insn32_if_mm 0x587e0056 | (\cs << 11)
	move	\rd, $1
	.set	pop
	.endm

.macro	_ctcmsa	cd, rs
	.set	push
	.set	noat
	SET_HARDFLOAT
	move	$1, \rs
	insn_if_mips 0x783e0819 | (\cd << 6)
	insn32_if_mm 0x583e0816 | (\cd << 6)
	.set	pop
	.endm

.macro	ld_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000820 | (\wd << 6)
	insn32_if_mm 0x58000807 | (\wd << 6)
	.set	pop
	.endm

.macro	ld_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000821 | (\wd << 6)
	insn32_if_mm 0x58000817 | (\wd << 6)
	.set	pop
	.endm

.macro	ld_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000822 | (\wd << 6)
	insn32_if_mm 0x58000827 | (\wd << 6)
	.set	pop
	.endm

.macro	ld_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000823 | (\wd << 6)
	insn32_if_mm 0x58000837 | (\wd << 6)
	.set	pop
	.endm

.macro	st_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000824 | (\wd << 6)
	insn32_if_mm 0x5800080f | (\wd << 6)
	.set	pop
	.endm

.macro	st_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000825 | (\wd << 6)
	insn32_if_mm 0x5800081f | (\wd << 6)
	.set	pop
	.endm

.macro	st_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000826 | (\wd << 6)
	insn32_if_mm 0x5800082f | (\wd << 6)
	.set	pop
	.endm

.macro	st_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000827 | (\wd << 6)
	insn32_if_mm 0x5800083f | (\wd << 6)
	.set	pop
	.endm

.macro	copy_s_w	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
	insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

.macro	copy_s_d	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
	insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

.macro	insert_w	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
	insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
	.set	pop
	.endm

.macro	insert_d	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
	insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
	.set	pop
	.endm
#endif

#ifdef TOOLCHAIN_SUPPORTS_MSA
#define FPR_BASE_OFFS	THREAD_FPR0
#define FPR_BASE	$1
#else
#define FPR_BASE_OFFS	0
#define FPR_BASE	\thread
#endif

.macro	msa_save_all	thread
	.set	push
	.set	noat
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	st_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	st_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	st_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	st_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	st_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	st_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	st_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	st_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	st_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	st_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	st_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	st_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	st_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	st_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	st_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	st_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	st_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	st_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	st_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	st_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	st_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	st_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	st_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	st_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	st_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	st_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	st_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	st_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	st_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	st_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	st_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	SET_HARDFLOAT
	_cfcmsa	$1, MSA_CSR
	sw	$1, THREAD_MSA_CSR(\thread)
	.set	pop
	.endm

.macro	msa_restore_all	thread
	.set	push
	.set	noat
	SET_HARDFLOAT
	lw	$1, THREAD_MSA_CSR(\thread)
	_ctcmsa	MSA_CSR, $1
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	ld_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	ld_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	ld_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	ld_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	ld_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	ld_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	ld_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	ld_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	ld_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	ld_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	ld_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	ld_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	ld_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	ld_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	ld_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	ld_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	ld_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	ld_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	ld_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	ld_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	ld_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	ld_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	.set pop
	.endm

#undef FPR_BASE_OFFS
#undef FPR_BASE

.macro	msa_init_upper wd
#ifdef CONFIG_64BIT
	insert_d \wd, 1
#else
	insert_w \wd, 2
	insert_w \wd, 3
#endif
	.endm

.macro	msa_init_all_upper
	.set	push
	.set	noat
	SET_HARDFLOAT
	not	$1, zero
	msa_init_upper	0
	msa_init_upper	1
	msa_init_upper	2
	msa_init_upper	3
	msa_init_upper	4
	msa_init_upper	5
	msa_init_upper	6
	msa_init_upper	7
	msa_init_upper	8
	msa_init_upper	9
	msa_init_upper	10
	msa_init_upper	11
	msa_init_upper	12
	msa_init_upper	13
	msa_init_upper	14
	msa_init_upper	15
	msa_init_upper	16
	msa_init_upper	17
	msa_init_upper	18
	msa_init_upper	19
	msa_init_upper	20
	msa_init_upper	21
	msa_init_upper	22
	msa_init_upper	23
	msa_init_upper	24
	msa_init_upper	25
	msa_init_upper	26
	msa_init_upper	27
	msa_init_upper	28
	msa_init_upper	29
	msa_init_upper	30
	msa_init_upper	31
	.set	pop
	.endm

#endif /* _ASM_ASMMACRO_H */

cmd: