FM / asm

/usr/src/linux-headers-5.15.0-181/arch/mips/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/mips/include/asm

Name	Size	Mode	Actions
dec/	-	0755	rm
fw/	-	0755	rm
ip32/	-	0755	rm
mach-ar7/	-	0755	rm
mach-ath25/	-	0755	rm
mach-ath79/	-	0755	rm
mach-au1x00/	-	0755	rm
mach-bcm47xx/	-	0755	rm
mach-bcm63xx/	-	0755	rm
mach-bmips/	-	0755	rm
mach-cavium-octeon/	-	0755	rm
mach-cobalt/	-	0755	rm
mach-db1x00/	-	0755	rm
mach-dec/	-	0755	rm
mach-generic/	-	0755	rm
mach-ingenic/	-	0755	rm
mach-ip22/	-	0755	rm
mach-ip27/	-	0755	rm
mach-ip28/	-	0755	rm
mach-ip30/	-	0755	rm
mach-ip32/	-	0755	rm
mach-jazz/	-	0755	rm
mach-lantiq/	-	0755	rm
mach-loongson2ef/	-	0755	rm
mach-loongson32/	-	0755	rm
mach-loongson64/	-	0755	rm
mach-malta/	-	0755	rm
mach-n64/	-	0755	rm
mach-netlogic/	-	0755	rm
mach-pic32/	-	0755	rm
mach-ralink/	-	0755	rm
mach-rc32434/	-	0755	rm
mach-rm/	-	0755	rm
mach-sibyte/	-	0755	rm
mach-tx39xx/	-	0755	rm
mach-tx49xx/	-	0755	rm
mach-vr41xx/	-	0755	rm
mips-boards/	-	0755	rm
netlogic/	-	0755	rm
octeon/	-	0755	rm
pci/	-	0755	rm
sgi/	-	0755	rm
sibyte/	-	0755	rm
sn/	-	0755	rm
txx9/	-	0755	rm
vdso/	-	0755	rm
vr41xx/	-	0755	rm
xtalk/	-	0755	rm
abi.h	853	0644	edit dl rm
addrspace.h	4039	0644	edit dl rm
amon.h	409	0644	edit dl rm
arch_hweight.h	792	0644	edit dl rm
asm-eva.h	7343	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	228	0644	edit dl rm
asm.h	6688	0644	edit dl rm
asmmacro-32.h	2529	0644	edit dl rm
asmmacro-64.h	1254	0644	edit dl rm
asmmacro.h	14639	0644	edit dl rm
atomic.h	8299	0644	edit dl rm
barrier.h	3507	0644	edit dl rm
bcache.h	2086	0644	edit dl rm
bitops.h	10914	0644	edit dl rm
bitrev.h	608	0644	edit dl rm
bmips-spaces.h	268	0644	edit dl rm
bmips.h	3097	0644	edit dl rm
bootinfo.h	4928	0644	edit dl rm
branch.h	2503	0644	edit dl rm
break.h	787	0644	edit dl rm
bug.h	759	0644	edit dl rm
bugs.h	640	0644	edit dl rm
cache.h	527	0644	edit dl rm
cacheflush.h	4863	0644	edit dl rm
cacheops.h	3801	0644	edit dl rm
cdmm.h	3761	0644	edit dl rm
cevt-r4k.h	823	0644	edit dl rm
checksum.h	5743	0644	edit dl rm
clocksource.h	273	0644	edit dl rm
cmp.h	492	0644	edit dl rm
cmpxchg.h	8880	0644	edit dl rm
compat-signal.h	640	0644	edit dl rm
compat.h	3866	0644	edit dl rm
compiler.h	2669	0644	edit dl rm
cop2.h	1812	0644	edit dl rm
cpu-features.h	22752	0644	edit dl rm
cpu-info.h	6303	0644	edit dl rm
cpu-type.h	4256	0644	edit dl rm
cpu.h	16955	0644	edit dl rm
cpufeature.h	510	0644	edit dl rm
debug.h	447	0644	edit dl rm
delay.h	841	0644	edit dl rm
div64.h	2223	0644	edit dl rm
dma-direct.h	255	0644	edit dl rm
dma-mapping.h	365	0644	edit dl rm
dma.h	10161	0644	edit dl rm
dmi.h	547	0644	edit dl rm
ds1287.h	333	0644	edit dl rm
dsemul.h	3595	0644	edit dl rm
dsp.h	1747	0644	edit dl rm
edac.h	839	0644	edit dl rm
elf.h	15559	0644	edit dl rm
elfcore-compat.h	841	0644	edit dl rm
errno.h	429	0644	edit dl rm
eva.h	796	0644	edit dl rm
exec.h	579	0644	edit dl rm
extable.h	241	0644	edit dl rm
fb.h	372	0644	edit dl rm
fixmap.h	2219	0644	edit dl rm
floppy.h	1609	0644	edit dl rm
fpregdef.h	2726	0644	edit dl rm
fpu.h	7332	0644	edit dl rm
fpu_emulator.h	4844	0644	edit dl rm
ftrace.h	2659	0644	edit dl rm
futex.h	5241	0644	edit dl rm
ginvt.h	1056	0644	edit dl rm
gio_device.h	1411	0644	edit dl rm
gt64120.h	19218	0644	edit dl rm
hardirq.h	544	0644	edit dl rm
hazards.h	8673	0644	edit dl rm
highmem.h	1741	0644	edit dl rm
hpet.h	1974	0644	edit dl rm
hugetlb.h	2165	0644	edit dl rm
hw_irq.h	475	0644	edit dl rm
i8259.h	2440	0644	edit dl rm
ide.h	330	0644	edit dl rm
idle.h	727	0644	edit dl rm
inst.h	2398	0644	edit dl rm
io.h	17334	0644	edit dl rm
irq.h	2408	0644	edit dl rm
irqflags.h	4206	0644	edit dl rm
irq_cpu.h	427	0644	edit dl rm
irq_gt641xx.h	2074	0644	edit dl rm
irq_regs.h	540	0644	edit dl rm
isa-rev.h	556	0644	edit dl rm
isadep.h	603	0644	edit dl rm
jazz.h	8192	0644	edit dl rm
jazzdma.h	2826	0644	edit dl rm
jump_label.h	1571	0644	edit dl rm
Kbuild	414	0644	edit dl rm
kdebug.h	303	0644	edit dl rm
kexec.h	1490	0644	edit dl rm
kgdb.h	1222	0644	edit dl rm
kprobes.h	1727	0644	edit dl rm
kvm_host.h	30488	0644	edit dl rm
kvm_types.h	184	0644	edit dl rm
linkage.h	306	0644	edit dl rm
llsc.h	923	0644	edit dl rm
local.h	5473	0644	edit dl rm
maar.h	4270	0644	edit dl rm
machine.h	2795	0644	edit dl rm
mc146818-time.h	3779	0644	edit dl rm
mc146818rtc.h	450	0644	edit dl rm
mips-cm.h	16857	0644	edit dl rm
mips-cpc.h	5766	0644	edit dl rm
mips-cps.h	6494	0644	edit dl rm
mips-gic.h	12387	0644	edit dl rm
mips-r2-to-r6-emul.h	2095	0644	edit dl rm
mipsmtregs.h	11171	0644	edit dl rm
mipsprom.h	2146	0644	edit dl rm
mipsregs.h	96792	0644	edit dl rm
mips_mt.h	707	0644	edit dl rm
mmiowb.h	197	0644	edit dl rm
mmu.h	555	0644	edit dl rm
mmu_context.h	6205	0644	edit dl rm
mmzone.h	427	0644	edit dl rm
module.h	2388	0644	edit dl rm
msa.h	7525	0644	edit dl rm
msc01_ic.h	6709	0644	edit dl rm
paccess.h	3140	0644	edit dl rm
page.h	7610	0644	edit dl rm
pci.h	3902	0644	edit dl rm
perf_event.h	336	0644	edit dl rm
pgalloc.h	2571	0644	edit dl rm
pgtable-32.h	8149	0644	edit dl rm
pgtable-64.h	9709	0644	edit dl rm
pgtable-bits.h	7852	0644	edit dl rm
pgtable.h	18529	0644	edit dl rm
pm-cps.h	1515	0644	edit dl rm
pm.h	3871	0644	edit dl rm
prefetch.h	2148	0644	edit dl rm
processor.h	11321	0644	edit dl rm
prom.h	696	0644	edit dl rm
ptrace.h	5582	0644	edit dl rm
r4k-timer.h	604	0644	edit dl rm
r4kcache.h	11373	0644	edit dl rm
reboot.h	440	0644	edit dl rm
reg.h	26	0644	edit dl rm
regdef.h	2693	0644	edit dl rm
rtlx.h	2148	0644	edit dl rm
seccomp.h	810	0644	edit dl rm
setup.h	941	0644	edit dl rm
sgialib.h	1743	0644	edit dl rm
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shmparam.h	352	0644	edit dl rm
sigcontext.h	1060	0644	edit dl rm
signal.h	1042	0644	edit dl rm
sim.h	2070	0644	edit dl rm
smp-cps.h	998	0644	edit dl rm
smp-ops.h	2476	0644	edit dl rm
smp.h	3696	0644	edit dl rm
sni.h	7495	0644	edit dl rm
socket.h	1377	0644	edit dl rm
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spinlock.h	822	0644	edit dl rm
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string.h	692	0644	edit dl rm
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time.h	1617	0644	edit dl rm
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topology.h	619	0644	edit dl rm
traps.h	1229	0644	edit dl rm
txx9irq.h	743	0644	edit dl rm
txx9pio.h	592	0644	edit dl rm
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types.h	459	0644	edit dl rm
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uasm.h	9578	0644	edit dl rm
unaligned-emul.h	26856	0644	edit dl rm
unistd.h	1860	0644	edit dl rm
unroll.h	2860	0644	edit dl rm
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vga.h	1291	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
vpe.h	2843	0644	edit dl rm
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watch.h	827	0644	edit dl rm
wbflush.h	694	0644	edit dl rm
yamon-dt.h	1717	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/mips/include/asm/r4kcache.h (11373B)

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Inline assembly cache operations.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
 */
#ifndef _ASM_R4KCACHE_H
#define _ASM_R4KCACHE_H

#include <linux/stringify.h>

#include <asm/asm.h>
#include <asm/asm-eva.h>
#include <asm/cacheops.h>
#include <asm/compiler.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/mipsmtregs.h>
#include <asm/mmzone.h>
#include <asm/unroll.h>

extern void (*r4k_blast_dcache)(void);
extern void (*r4k_blast_icache)(void);

/*
 * This macro return a properly sign-extended address suitable as base address
 * for indexed cache operations.  Two issues here:
 *
 *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
 *    the index bits from the virtual address.	This breaks with tradition
 *    set by the R4000.	 To keep unpleasant surprises from happening we pick
 *    an address in KSEG0 / CKSEG0.
 *  - We need a properly sign extended address for 64-bit code.	 To get away
 *    without ifdefs we let the compiler do it by a type cast.
 */
#define INDEX_BASE	CKSEG0

#define _cache_op(insn, op, addr)					\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noreorder				\n"	\
	"	.set "MIPS_ISA_ARCH_LEVEL"			\n"	\
	"	" insn("%0", "%1") "				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "i" (op), "R" (*(unsigned char *)(addr)))

#define cache_op(op, addr)						\
	_cache_op(kernel_cache, op, addr)

static inline void flush_icache_line_indexed(unsigned long addr)
{
	cache_op(Index_Invalidate_I, addr);
}

static inline void flush_dcache_line_indexed(unsigned long addr)
{
	cache_op(Index_Writeback_Inv_D, addr);
}

static inline void flush_scache_line_indexed(unsigned long addr)
{
	cache_op(Index_Writeback_Inv_SD, addr);
}

static inline void flush_icache_line(unsigned long addr)
{
	switch (boot_cpu_type()) {
	case CPU_LOONGSON2EF:
		cache_op(Hit_Invalidate_I_Loongson2, addr);
		break;

default:
		cache_op(Hit_Invalidate_I, addr);
		break;
	}
}

static inline void flush_dcache_line(unsigned long addr)
{
	cache_op(Hit_Writeback_Inv_D, addr);
}

static inline void invalidate_dcache_line(unsigned long addr)
{
	cache_op(Hit_Invalidate_D, addr);
}

static inline void invalidate_scache_line(unsigned long addr)
{
	cache_op(Hit_Invalidate_SD, addr);
}

static inline void flush_scache_line(unsigned long addr)
{
	cache_op(Hit_Writeback_Inv_SD, addr);
}

#ifdef CONFIG_EVA

#define protected_cache_op(op, addr)				\
({								\
	int __err = 0;						\
	__asm__ __volatile__(					\
	"	.set	push			\n"		\
	"	.set	noreorder		\n"		\
	"	.set	mips0			\n"		\
	"	.set	eva			\n"		\
	"1:	cachee	%1, (%2)		\n"		\
	"2:	.insn				\n"		\
	"	.set	pop			\n"		\
	"	.section .fixup,\"ax\"		\n"		\
	"3:	li	%0, %3			\n"		\
	"	j	2b			\n"		\
	"	.previous			\n"		\
	"	.section __ex_table,\"a\"	\n"		\
	"	"STR(PTR_WD)" 1b, 3b		\n"		\
	"	.previous"					\
	: "+r" (__err)						\
	: "i" (op), "r" (addr), "i" (-EFAULT));			\
	__err;							\
})
#else

#define protected_cache_op(op, addr)				\
({								\
	int __err = 0;						\
	__asm__ __volatile__(					\
	"	.set	push			\n"		\
	"	.set	noreorder		\n"		\
	"	.set "MIPS_ISA_ARCH_LEVEL"	\n"		\
	"1:	cache	%1, (%2)		\n"		\
	"2:	.insn				\n"		\
	"	.set	pop			\n"		\
	"	.section .fixup,\"ax\"		\n"		\
	"3:	li	%0, %3			\n"		\
	"	j	2b			\n"		\
	"	.previous			\n"		\
	"	.section __ex_table,\"a\"	\n"		\
	"	"STR(PTR_WD)" 1b, 3b		\n"		\
	"	.previous"					\
	: "+r" (__err)						\
	: "i" (op), "r" (addr), "i" (-EFAULT));			\
	__err;							\
})
#endif

/*
 * The next two are for badland addresses like signal trampolines.
 */
static inline int protected_flush_icache_line(unsigned long addr)
{
	switch (boot_cpu_type()) {
	case CPU_LOONGSON2EF:
		return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);

default:
		return protected_cache_op(Hit_Invalidate_I, addr);
	}
}

/*
 * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
 * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
 * caches.  We're talking about one cacheline unnecessarily getting invalidated
 * here so the penalty isn't overly hard.
 */
static inline int protected_writeback_dcache_line(unsigned long addr)
{
	return protected_cache_op(Hit_Writeback_Inv_D, addr);
}

static inline int protected_writeback_scache_line(unsigned long addr)
{
	return protected_cache_op(Hit_Writeback_Inv_SD, addr);
}

/*
 * This one is RM7000-specific
 */
static inline void invalidate_tcache_page(unsigned long addr)
{
	cache_op(Page_Invalidate_T, addr);
}

#define cache_unroll(times, insn, op, addr, lsize) do {			\
	int i = 0;							\
	unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize)));	\
} while (0)

/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
static inline void extra##blast_##pfx##cache##lsize(void)		\
{									\
	unsigned long start = INDEX_BASE;				\
	unsigned long end = start + current_cpu_data.desc.waysize;	\
	unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;	\
	unsigned long ws_end = current_cpu_data.desc.ways <<		\
			       current_cpu_data.desc.waybit;		\
	unsigned long ws, addr;						\
									\
	for (ws = 0; ws < ws_end; ws += ws_inc)				\
		for (addr = start; addr < end; addr += lsize * 32)	\
			cache_unroll(32, kernel_cache, indexop,		\
				     addr | ws, lsize);			\
}									\
									\
static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
{									\
	unsigned long start = page;					\
	unsigned long end = page + PAGE_SIZE;				\
									\
	do {								\
		cache_unroll(32, kernel_cache, hitop, start, lsize);	\
		start += lsize * 32;					\
	} while (start < end);						\
}									\
									\
static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
{									\
	unsigned long indexmask = current_cpu_data.desc.waysize - 1;	\
	unsigned long start = INDEX_BASE + (page & indexmask);		\
	unsigned long end = start + PAGE_SIZE;				\
	unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;	\
	unsigned long ws_end = current_cpu_data.desc.ways <<		\
			       current_cpu_data.desc.waybit;		\
	unsigned long ws, addr;						\
									\
	for (ws = 0; ws < ws_end; ws += ws_inc)				\
		for (addr = start; addr < end; addr += lsize * 32)	\
			cache_unroll(32, kernel_cache, indexop,		\
				     addr | ws, lsize);			\
}

__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )

__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )

#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
{									\
	unsigned long start = page;					\
	unsigned long end = page + PAGE_SIZE;				\
									\
	do {								\
		cache_unroll(32, user_cache, hitop, start, lsize);	\
		start += lsize * 32;					\
	} while (start < end);						\
}

__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
			 16)
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
			 32)
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
			 64)
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)

/* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
						    unsigned long end)	\
{									\
	unsigned long lsize = cpu_##desc##_line_size();			\
	unsigned long addr = start & ~(lsize - 1);			\
	unsigned long aend = (end - 1) & ~(lsize - 1);			\
									\
	while (1) {							\
		prot##cache_op(hitop, addr);				\
		if (addr == aend)					\
			break;						\
		addr += lsize;						\
	}								\
}

__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
	protected_, loongson2_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
/* blast_inv_dcache_range */
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )

/* Currently, this is very specific to Loongson-3 */
#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)	\
static inline void blast_##pfx##cache##lsize##_node(long node)		\
{									\
	unsigned long start = CAC_BASE | nid_to_addrbase(node);		\
	unsigned long end = start + current_cpu_data.desc.waysize;	\
	unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;	\
	unsigned long ws_end = current_cpu_data.desc.ways <<		\
			       current_cpu_data.desc.waybit;		\
	unsigned long ws, addr;						\
									\
	for (ws = 0; ws < ws_end; ws += ws_inc)				\
		for (addr = start; addr < end; addr += lsize * 32)	\
			cache_unroll(32, kernel_cache, indexop,		\
				     addr | ws, lsize);			\
}

__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)

#endif /* _ASM_R4KCACHE_H */

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