FM / asm

/usr/src/linux-headers-5.15.0-181/arch/riscv/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/riscv/include/asm

Name	Size	Mode	Actions
vdso/	-	0755	rm
alternative-macros.h	4658	0644	edit dl rm
alternative.h	930	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	1040	0644	edit dl rm
asm.h	1558	0644	edit dl rm
atomic.h	11028	0644	edit dl rm
barrier.h	2458	0644	edit dl rm
bitops.h	5809	0644	edit dl rm
bug.h	2186	0644	edit dl rm
cache.h	516	0644	edit dl rm
cacheflush.h	1307	0644	edit dl rm
cacheinfo.h	511	0644	edit dl rm
clint.h	797	0644	edit dl rm
clocksource.h	136	0644	edit dl rm
cmpxchg.h	9537	0644	edit dl rm
cpu_ops.h	1494	0644	edit dl rm
csr.h	6062	0644	edit dl rm
current.h	940	0644	edit dl rm
delay.h	471	0644	edit dl rm
efi.h	1150	0644	edit dl rm
elf.h	2726	0644	edit dl rm
errata_list.h	1074	0644	edit dl rm
fence.h	279	0644	edit dl rm
fixmap.h	1806	0644	edit dl rm
ftrace.h	3086	0644	edit dl rm
futex.h	2906	0644	edit dl rm
gdb_xml.h	5601	0644	edit dl rm
hugetlb.h	360	0644	edit dl rm
hwcap.h	1245	0644	edit dl rm
image.h	1673	0644	edit dl rm
io.h	5322	0644	edit dl rm
irq.h	347	0644	edit dl rm
irqflags.h	1175	0644	edit dl rm
irq_work.h	225	0644	edit dl rm
jump_label.h	1440	0644	edit dl rm
kasan.h	1390	0644	edit dl rm
Kbuild	178	0644	edit dl rm
kdebug.h	158	0644	edit dl rm
kexec.h	1349	0644	edit dl rm
kfence.h	1312	0644	edit dl rm
kgdb.h	2494	0644	edit dl rm
kprobes.h	1136	0644	edit dl rm
linkage.h	267	0644	edit dl rm
mmio.h	5347	0644	edit dl rm
mmiowb.h	398	0644	edit dl rm
mmu.h	610	0644	edit dl rm
mmu_context.h	898	0644	edit dl rm
mmzone.h	266	0644	edit dl rm
module.h	2984	0644	edit dl rm
module.lds.h	207	0644	edit dl rm
numa.h	165	0644	edit dl rm
page.h	5264	0644	edit dl rm
parse_asm.h	7265	0644	edit dl rm
patch.h	314	0644	edit dl rm
pci.h	1062	0644	edit dl rm
perf_event.h	2204	0644	edit dl rm
pgalloc.h	1801	0644	edit dl rm
pgtable-32.h	498	0644	edit dl rm
pgtable-64.h	1898	0644	edit dl rm
pgtable-bits.h	1552	0644	edit dl rm
pgtable.h	18086	0644	edit dl rm
probes.h	563	0644	edit dl rm
processor.h	2138	0644	edit dl rm
ptdump.h	338	0644	edit dl rm
ptrace.h	4304	0644	edit dl rm
sbi.h	4223	0644	edit dl rm
seccomp.h	504	0644	edit dl rm
sections.h	883	0644	edit dl rm
set_memory.h	1869	0644	edit dl rm
smp.h	2427	0644	edit dl rm
soc.h	627	0644	edit dl rm
sparsemem.h	263	0644	edit dl rm
spinlock.h	2508	0644	edit dl rm
spinlock_types.h	530	0644	edit dl rm
stackprotector.h	768	0644	edit dl rm
stacktrace.h	496	0644	edit dl rm
string.h	1078	0644	edit dl rm
switch_to.h	2107	0644	edit dl rm
syscall.h	2163	0644	edit dl rm
thread_info.h	3955	0644	edit dl rm
timex.h	1859	0644	edit dl rm
tlb.h	403	0644	edit dl rm
tlbflush.h	1803	0644	edit dl rm
uaccess.h	13955	0644	edit dl rm
unistd.h	328	0644	edit dl rm
uprobes.h	828	0644	edit dl rm
vdso.h	868	0644	edit dl rm
vendorid_list.h	172	0644	edit dl rm
vermagic.h	213	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm
word-at-a-time.h	1104	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/riscv/include/asm/io.h (5322B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
 *   which was based on arch/arm/include/io.h
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 * Copyright (C) 2014 Regents of the University of California
 */

#ifndef _ASM_RISCV_IO_H
#define _ASM_RISCV_IO_H

#include <linux/types.h>
#include <linux/pgtable.h>
#include <asm/mmiowb.h>
#include <asm/early_ioremap.h>

/*
 * MMIO access functions are separated out to break dependency cycles
 * when using {read,write}* fns in low-level headers
 */
#include <asm/mmio.h>

/*
 *  I/O port access constants.
 */
#ifdef CONFIG_MMU
#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
#define PCI_IOBASE		((void __iomem *)PCI_IO_START)
#endif /* CONFIG_MMU */

/*
 * Emulation routines for the port-mapped IO space used by some PCI drivers.
 * These are defined as being "fully synchronous", but also "not guaranteed to
 * be fully ordered with respect to other memory and I/O operations".  We're
 * going to be on the safe side here and just make them:
 *  - Fully ordered WRT each other, by bracketing them with two fences.  The
 *    outer set contains both I/O so inX is ordered with outX, while the inner just
 *    needs the type of the access (I for inX and O for outX).
 *  - Ordered in the same manner as readX/writeX WRT memory by subsuming their
 *    fences.
 *  - Ordered WRT timer reads, so udelay and friends don't get elided by the
 *    implementation.
 * Note that there is no way to actually enforce that outX is a non-posted
 * operation on RISC-V, but hopefully the timer ordering constraint is
 * sufficient to ensure this works sanely on controllers that support I/O
 * writes.
 */
#define __io_pbr()	__asm__ __volatile__ ("fence io,i"  : : : "memory");
#define __io_par(v)	__asm__ __volatile__ ("fence i,ior" : : : "memory");
#define __io_pbw()	__asm__ __volatile__ ("fence iow,o" : : : "memory");
#define __io_paw()	__asm__ __volatile__ ("fence o,io"  : : : "memory");

/*
 * Accesses from a single hart to a single I/O address must be ordered.  This
 * allows us to use the raw read macros, but we still need to fence before and
 * after the block to ensure ordering WRT other macros.  These are defined to
 * perform host-endian accesses so we use __raw instead of __cpu.
 */
#define __io_reads_ins(port, ctype, len, bfence, afence)			\
	static inline void __ ## port ## len(const volatile void __iomem *addr,	\
					     void *buffer,			\
					     unsigned int count)		\
	{									\
		bfence;								\
		if (count) {							\
			ctype *buf = buffer;					\
										\
			do {							\
				ctype x = __raw_read ## len(addr);		\
				*buf++ = x;					\
			} while (--count);					\
		}								\
		afence;								\
	}

#define __io_writes_outs(port, ctype, len, bfence, afence)			\
	static inline void __ ## port ## len(volatile void __iomem *addr,	\
					     const void *buffer,		\
					     unsigned int count)		\
	{									\
		bfence;								\
		if (count) {							\
			const ctype *buf = buffer;				\
										\
			do {							\
				__raw_write ## len(*buf++, addr);		\
			} while (--count);					\
		}								\
		afence;								\
	}

__io_reads_ins(reads,  u8, b, __io_br(), __io_ar(addr))
__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
#define readsb(addr, buffer, count) __readsb(addr, buffer, count)
#define readsw(addr, buffer, count) __readsw(addr, buffer, count)
#define readsl(addr, buffer, count) __readsl(addr, buffer, count)

__io_reads_ins(ins,  u8, b, __io_pbr(), __io_par(addr))
__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
#define insb(addr, buffer, count) __insb(PCI_IOBASE + (addr), buffer, count)
#define insw(addr, buffer, count) __insw(PCI_IOBASE + (addr), buffer, count)
#define insl(addr, buffer, count) __insl(PCI_IOBASE + (addr), buffer, count)

__io_writes_outs(writes,  u8, b, __io_bw(), __io_aw())
__io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
__io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
#define writesb(addr, buffer, count) __writesb(addr, buffer, count)
#define writesw(addr, buffer, count) __writesw(addr, buffer, count)
#define writesl(addr, buffer, count) __writesl(addr, buffer, count)

__io_writes_outs(outs,  u8, b, __io_pbw(), __io_paw())
__io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
__io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
#define outsb(addr, buffer, count) __outsb(PCI_IOBASE + (addr), buffer, count)
#define outsw(addr, buffer, count) __outsw(PCI_IOBASE + (addr), buffer, count)
#define outsl(addr, buffer, count) __outsl(PCI_IOBASE + (addr), buffer, count)

#ifdef CONFIG_64BIT
__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
#define readsq(addr, buffer, count) __readsq(addr, buffer, count)

__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
#define insq(addr, buffer, count) __insq(PCI_IOBASE + (addr), buffer, count)

__io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
#define writesq(addr, buffer, count) __writesq(addr, buffer, count)

__io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
#define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
#endif

#include <asm-generic/io.h>

#endif /* _ASM_RISCV_IO_H */

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