FM / asm

/usr/src/linux-headers-5.15.0-181/arch/sparc/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/sparc/include/asm

Name	Size	Mode	Actions
adi.h	138	0644	edit dl rm
adi_64.h	812	0644	edit dl rm
agp.h	434	0644	edit dl rm
apb.h	1082	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	729	0644	edit dl rm
asm.h	1101	0644	edit dl rm
asmmacro.h	1183	0644	edit dl rm
atomic.h	219	0644	edit dl rm
atomic_32.h	1760	0644	edit dl rm
atomic_64.h	1849	0644	edit dl rm
auxio.h	310	0644	edit dl rm
auxio_32.h	2615	0644	edit dl rm
auxio_64.h	3253	0644	edit dl rm
backoff.h	2756	0644	edit dl rm
barrier.h	223	0644	edit dl rm
barrier_32.h	160	0644	edit dl rm
barrier_64.h	2004	0644	edit dl rm
bbc.h	9996	0644	edit dl rm
bitext.h	631	0644	edit dl rm
bitops.h	219	0644	edit dl rm
bitops_32.h	2853	0644	edit dl rm
bitops_64.h	1675	0644	edit dl rm
btext.h	145	0644	edit dl rm
bug.h	588	0644	edit dl rm
cache.h	630	0644	edit dl rm
cacheflush.h	373	0644	edit dl rm
cacheflush_32.h	1951	0644	edit dl rm
cacheflush_64.h	2557	0644	edit dl rm
cachetlb_32.h	882	0644	edit dl rm
chafsr.h	9710	0644	edit dl rm
checksum.h	331	0644	edit dl rm
checksum_32.h	5791	0644	edit dl rm
checksum_64.h	3855	0644	edit dl rm
chmctrl.h	8096	0644	edit dl rm
clock.h	231	0644	edit dl rm
clocksource.h	407	0644	edit dl rm
cmpxchg.h	223	0644	edit dl rm
cmpxchg_32.h	2483	0644	edit dl rm
cmpxchg_64.h	5288	0644	edit dl rm
compat.h	3890	0644	edit dl rm
compat_signal.h	565	0644	edit dl rm
contregs.h	1941	0644	edit dl rm
cpudata.h	378	0644	edit dl rm
cpudata_32.h	729	0644	edit dl rm
cpudata_64.h	1153	0644	edit dl rm
cpu_type.h	579	0644	edit dl rm
current.h	991	0644	edit dl rm
dcr.h	728	0644	edit dl rm
dcu.h	1520	0644	edit dl rm
delay.h	215	0644	edit dl rm
delay_32.h	907	0644	edit dl rm
delay_64.h	403	0644	edit dl rm
device.h	565	0644	edit dl rm
dma-mapping.h	336	0644	edit dl rm
dma.h	4989	0644	edit dl rm
ebus_dma.h	1098	0644	edit dl rm
ecc.h	4448	0644	edit dl rm
eeprom.h	254	0644	edit dl rm
elf.h	207	0644	edit dl rm
elf_32.h	3267	0644	edit dl rm
elf_64.h	6848	0644	edit dl rm
estate.h	2287	0644	edit dl rm
extable.h	723	0644	edit dl rm
fb.h	680	0644	edit dl rm
fbio.h	2315	0644	edit dl rm
fhc.h	4533	0644	edit dl rm
floppy.h	219	0644	edit dl rm
floppy_32.h	9796	0644	edit dl rm
floppy_64.h	19392	0644	edit dl rm
fpumacro.h	710	0644	edit dl rm
ftrace.h	801	0644	edit dl rm
futex.h	215	0644	edit dl rm
futex_32.h	82	0644	edit dl rm
futex_64.h	2160	0644	edit dl rm
hardirq.h	223	0644	edit dl rm
hardirq_32.h	334	0644	edit dl rm
hardirq_64.h	412	0644	edit dl rm
head.h	211	0644	edit dl rm
head_32.h	2617	0644	edit dl rm
head_64.h	2184	0644	edit dl rm
hibernate.h	421	0644	edit dl rm
highmem.h	1966	0644	edit dl rm
hugetlb.h	1592	0644	edit dl rm
hvtramp.h	782	0644	edit dl rm
hw_irq.h	88	0644	edit dl rm
hypervisor.h	117649	0644	edit dl rm
ide.h	2222	0644	edit dl rm
idprom.h	656	0644	edit dl rm
intr_queue.h	794	0644	edit dl rm
io-unit.h	2469	0644	edit dl rm
io.h	620	0644	edit dl rm
ioctls.h	358	0644	edit dl rm
iommu-common.h	1445	0644	edit dl rm
iommu.h	215	0644	edit dl rm
iommu_32.h	5865	0644	edit dl rm
iommu_64.h	2489	0644	edit dl rm
io_32.h	3430	0644	edit dl rm
io_64.h	11076	0644	edit dl rm
irq.h	207	0644	edit dl rm
irqflags.h	227	0644	edit dl rm
irqflags_32.h	1058	0644	edit dl rm
irqflags_64.h	1952	0644	edit dl rm
irq_32.h	526	0644	edit dl rm
irq_64.h	3105	0644	edit dl rm
jump_label.h	1036	0644	edit dl rm
Kbuild	177	0644	edit dl rm
kdebug.h	219	0644	edit dl rm
kdebug_32.h	2041	0644	edit dl rm
kdebug_64.h	393	0644	edit dl rm
kgdb.h	1014	0644	edit dl rm
kprobes.h	1410	0644	edit dl rm
ldc.h	4475	0644	edit dl rm
leon.h	7844	0644	edit dl rm
leon_amba.h	8280	0644	edit dl rm
leon_pci.h	512	0644	edit dl rm
lsu.h	1062	0644	edit dl rm
machines.h	1540	0644	edit dl rm
mbus.h	2996	0644	edit dl rm
mc146818rtc.h	298	0644	edit dl rm
mc146818rtc_32.h	699	0644	edit dl rm
mc146818rtc_64.h	689	0644	edit dl rm
mdesc.h	3066	0644	edit dl rm
memctrl.h	311	0644	edit dl rm
mman.h	2633	0644	edit dl rm
mmu.h	207	0644	edit dl rm
mmu_32.h	209	0644	edit dl rm
mmu_64.h	3967	0644	edit dl rm
mmu_context.h	239	0644	edit dl rm
mmu_context_32.h	1082	0644	edit dl rm
mmu_context_64.h	5481	0644	edit dl rm
mmzone.h	363	0644	edit dl rm
mxcc.h	4429	0644	edit dl rm
nmi.h	354	0644	edit dl rm
ns87303.h	3299	0644	edit dl rm
obio.h	6410	0644	edit dl rm
openprom.h	7475	0644	edit dl rm
oplib.h	215	0644	edit dl rm
oplib_32.h	6062	0644	edit dl rm
oplib_64.h	8357	0644	edit dl rm
page.h	274	0644	edit dl rm
page_32.h	3826	0644	edit dl rm
page_64.h	4753	0644	edit dl rm
parport.h	5819	0644	edit dl rm
pbm.h	1505	0644	edit dl rm
pci.h	1367	0644	edit dl rm
pcic.h	5904	0644	edit dl rm
pcr.h	1893	0644	edit dl rm
percpu.h	219	0644	edit dl rm
percpu_32.h	168	0644	edit dl rm
percpu_64.h	541	0644	edit dl rm
perf_event.h	802	0644	edit dl rm
pgalloc.h	223	0644	edit dl rm
pgalloc_32.h	1823	0644	edit dl rm
pgalloc_64.h	2764	0644	edit dl rm
pgtable.h	223	0644	edit dl rm
pgtable_32.h	11021	0644	edit dl rm
pgtable_64.h	32369	0644	edit dl rm
pgtsrmmu.h	4879	0644	edit dl rm
pil.h	1109	0644	edit dl rm
processor.h	231	0644	edit dl rm
processor_32.h	2836	0644	edit dl rm
processor_64.h	7577	0644	edit dl rm
prom.h	1776	0644	edit dl rm
psr.h	1414	0644	edit dl rm
ptrace.h	4294	0644	edit dl rm
qrwlock.h	205	0644	edit dl rm
qspinlock.h	215	0644	edit dl rm
ross.h	5655	0644	edit dl rm
sbi.h	3425	0644	edit dl rm
scratchpad.h	547	0644	edit dl rm
seccomp.h	225	0644	edit dl rm
sections.h	289	0644	edit dl rm
setup.h	1552	0644	edit dl rm
sfafsr.h	3216	0644	edit dl rm
sfp-machine.h	239	0644	edit dl rm
sfp-machine_32.h	6954	0644	edit dl rm
sfp-machine_64.h	3178	0644	edit dl rm
shmparam.h	227	0644	edit dl rm
shmparam_32.h	253	0644	edit dl rm
shmparam_64.h	306	0644	edit dl rm
sigcontext.h	2616	0644	edit dl rm
signal.h	351	0644	edit dl rm
smp.h	207	0644	edit dl rm
smp_32.h	3368	0644	edit dl rm
smp_64.h	1791	0644	edit dl rm
sparsemem.h	295	0644	edit dl rm
spinlock.h	227	0644	edit dl rm
spinlock_32.h	4324	0644	edit dl rm
spinlock_64.h	409	0644	edit dl rm
spinlock_types.h	549	0644	edit dl rm
spitfire.h	9967	0644	edit dl rm
stacktrace.h	166	0644	edit dl rm
starfire.h	418	0644	edit dl rm
string.h	1254	0644	edit dl rm
string_32.h	405	0644	edit dl rm
string_64.h	409	0644	edit dl rm
sunbpp.h	3346	0644	edit dl rm
swift.h	3147	0644	edit dl rm
switch_to.h	231	0644	edit dl rm
switch_to_32.h	3616	0644	edit dl rm
switch_to_64.h	2640	0644	edit dl rm
syscall.h	3464	0644	edit dl rm
syscalls.h	299	0644	edit dl rm
termbits.h	198	0644	edit dl rm
termios.h	5063	0644	edit dl rm
thread_info.h	239	0644	edit dl rm
thread_info_32.h	3773	0644	edit dl rm
thread_info_64.h	8195	0644	edit dl rm
timer.h	215	0644	edit dl rm
timer_32.h	1211	0644	edit dl rm
timer_64.h	2448	0644	edit dl rm
timex.h	215	0644	edit dl rm
timex_32.h	266	0644	edit dl rm
timex_64.h	423	0644	edit dl rm
tlb.h	207	0644	edit dl rm
tlbflush.h	227	0644	edit dl rm
tlbflush_32.h	621	0644	edit dl rm
tlbflush_64.h	1776	0644	edit dl rm
tlb_32.h	138	0644	edit dl rm
tlb_64.h	1056	0644	edit dl rm
topology.h	227	0644	edit dl rm
topology_32.h	170	0644	edit dl rm
topology_64.h	1546	0644	edit dl rm
traps.h	577	0644	edit dl rm
trap_block.h	6786	0644	edit dl rm
tsb.h	12457	0644	edit dl rm
tsunami.h	1890	0644	edit dl rm
ttable.h	20827	0644	edit dl rm
turbosparc.h	3866	0644	edit dl rm
uaccess.h	390	0644	edit dl rm
uaccess_32.h	7032	0644	edit dl rm
uaccess_64.h	6142	0644	edit dl rm
unistd.h	1797	0644	edit dl rm
upa.h	3808	0644	edit dl rm
uprobes.h	1304	0644	edit dl rm
user.h	102	0644	edit dl rm
vaddrs.h	2066	0644	edit dl rm
vdso.h	491	0644	edit dl rm
vga.h	964	0644	edit dl rm
viking.h	8341	0644	edit dl rm
vio.h	12097	0644	edit dl rm
visasm.h	1544	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm
vvar.h	1577	0644	edit dl rm
winmacro.h	4767	0644	edit dl rm
xor.h	207	0644	edit dl rm
xor_32.h	7086	0644	edit dl rm
xor_64.h	2156	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/sparc/include/asm/bbc.h (9996B)

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
 *        systems.
 *
 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
 */

#ifndef _SPARC64_BBC_H
#define _SPARC64_BBC_H

/* Register sizes are indicated by "B" (Byte, 1-byte),
 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
 * "Q" (Quad, 8 bytes) inside brackets.
 */

#define BBC_AID		0x00	/* [B] Agent ID			*/
#define BBC_DEVP	0x01	/* [B] Device Present		*/
#define BBC_ARB		0x02	/* [B] Arbitration		*/
#define BBC_QUIESCE	0x03	/* [B] Quiesce			*/
#define BBC_WDACTION	0x04	/* [B] Watchdog Action		*/
#define BBC_SPG		0x06	/* [B] Soft POR Gen		*/
#define BBC_SXG		0x07	/* [B] Soft XIR Gen		*/
#define BBC_PSRC	0x08	/* [W] POR Source		*/
#define BBC_XSRC	0x0c	/* [B] XIR Source		*/
#define BBC_CSC		0x0d	/* [B] Clock Synthesizers Control*/
#define BBC_ES_CTRL	0x0e	/* [H] Energy Star Control	*/
#define BBC_ES_ACT	0x10	/* [W] E* Assert Change Time	*/
#define BBC_ES_DACT	0x14	/* [B] E* De-Assert Change Time	*/
#define BBC_ES_DABT	0x15	/* [B] E* De-Assert Bypass Time	*/
#define BBC_ES_ABT	0x16	/* [H] E* Assert Bypass Time	*/
#define BBC_ES_PST	0x18	/* [W] E* PLL Settle Time	*/
#define BBC_ES_FSL	0x1c	/* [W] E* Frequency Switch Latency*/
#define BBC_EBUST	0x20	/* [Q] EBUS Timing		*/
#define BBC_JTAG_CMD	0x28	/* [W] JTAG+ Command		*/
#define BBC_JTAG_CTRL	0x2c	/* [B] JTAG+ Control		*/
#define BBC_I2C_SEL	0x2d	/* [B] I2C Selection		*/
#define BBC_I2C_0_S1	0x2e	/* [B] I2C ctrlr-0 reg S1	*/
#define BBC_I2C_0_S0	0x2f	/* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
#define BBC_I2C_1_S1	0x30	/* [B] I2C ctrlr-1 reg S1	*/
#define BBC_I2C_1_S0	0x31	/* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
#define BBC_KBD_BEEP	0x32	/* [B] Keyboard Beep		*/
#define BBC_KBD_BCNT	0x34	/* [W] Keyboard Beep Counter	*/

#define BBC_REGS_SIZE	0x40

/* There is a 2K scratch ram area at offset 0x80000 but I doubt
 * we will use it for anything.
 */

/* Agent ID register.  This register shows the Safari Agent ID
 * for the processors.  The value returned depends upon which
 * cpu is reading the register.
 */
#define BBC_AID_ID	0x07	/* Safari ID		*/
#define BBC_AID_RESV	0xf8	/* Reserved		*/

/* Device Present register.  One can determine which cpus are actually
 * present in the machine by interrogating this register.
 */
#define BBC_DEVP_CPU0	0x01	/* Processor 0 present	*/
#define BBC_DEVP_CPU1	0x02	/* Processor 1 present	*/
#define BBC_DEVP_CPU2	0x04	/* Processor 2 present	*/
#define BBC_DEVP_CPU3	0x08	/* Processor 3 present	*/
#define BBC_DEVP_RESV	0xf0	/* Reserved		*/

/* Arbitration register.  This register is used to block access to
 * the BBC from a particular cpu.
 */
#define BBC_ARB_CPU0	0x01	/* Enable cpu 0 BBC arbitratrion */
#define BBC_ARB_CPU1	0x02	/* Enable cpu 1 BBC arbitratrion */
#define BBC_ARB_CPU2	0x04	/* Enable cpu 2 BBC arbitratrion */
#define BBC_ARB_CPU3	0x08	/* Enable cpu 3 BBC arbitratrion */
#define BBC_ARB_RESV	0xf0	/* Reserved			 */

/* Quiesce register.  Bus and BBC segments for cpus can be disabled
 * with this register, ie. for hot plugging.
 */
#define BBC_QUIESCE_S02	0x01	/* Quiesce Safari segment for cpu 0 and 2 */
#define BBC_QUIESCE_S13	0x02	/* Quiesce Safari segment for cpu 1 and 3 */
#define BBC_QUIESCE_B02	0x04	/* Quiesce BBC segment for cpu 0 and 2    */
#define BBC_QUIESCE_B13	0x08	/* Quiesce BBC segment for cpu 1 and 3    */
#define BBC_QUIESCE_FD0 0x10	/* Disable Fatal_Error[0] reporting	  */
#define BBC_QUIESCE_FD1 0x20	/* Disable Fatal_Error[1] reporting	  */
#define BBC_QUIESCE_FD2 0x40	/* Disable Fatal_Error[2] reporting	  */
#define BBC_QUIESCE_FD3 0x80	/* Disable Fatal_Error[3] reporting	  */

/* Watchdog Action register.  When the watchdog device timer expires
 * a line is enabled to the BBC.  The action BBC takes when this line
 * is asserted can be controlled by this regiser.
 */
#define BBC_WDACTION_RST  0x01	/* When set, watchdog causes system reset.
				 * When clear, BBC ignores watchdog signal.
				 */
#define BBC_WDACTION_RESV 0xfe	/* Reserved */

/* Soft_POR_GEN register.  The POR (Power On Reset) signal may be asserted
 * for specific processors or all processors via this register.
 */
#define BBC_SPG_CPU0	0x01 /* Assert POR for processor 0	*/
#define BBC_SPG_CPU1	0x02 /* Assert POR for processor 1	*/
#define BBC_SPG_CPU2	0x04 /* Assert POR for processor 2	*/
#define BBC_SPG_CPU3	0x08 /* Assert POR for processor 3	*/
#define BBC_SPG_CPUALL	0x10 /* Reset all processors and reset
			      * the entire system.
			      */
#define BBC_SPG_RESV	0xe0 /* Reserved			*/

/* Soft_XIR_GEN register.  The XIR (eXternally Initiated Reset) signal
 * may be asserted to specific processors via this register.
 */
#define BBC_SXG_CPU0	0x01 /* Assert XIR for processor 0	*/
#define BBC_SXG_CPU1	0x02 /* Assert XIR for processor 1	*/
#define BBC_SXG_CPU2	0x04 /* Assert XIR for processor 2	*/
#define BBC_SXG_CPU3	0x08 /* Assert XIR for processor 3	*/
#define BBC_SXG_RESV	0xf0 /* Reserved			*/

/* POR Source register.  One may identify the cause of the most recent
 * reset by reading this register.
 */
#define BBC_PSRC_SPG0	0x0001 /* CPU 0 reset via BBC_SPG register	*/
#define BBC_PSRC_SPG1	0x0002 /* CPU 1 reset via BBC_SPG register	*/
#define BBC_PSRC_SPG2	0x0004 /* CPU 2 reset via BBC_SPG register	*/
#define BBC_PSRC_SPG3	0x0008 /* CPU 3 reset via BBC_SPG register	*/
#define BBC_PSRC_SPGSYS	0x0010 /* System reset via BBC_SPG register	*/
#define BBC_PSRC_JTAG	0x0020 /* System reset via JTAG+		*/
#define BBC_PSRC_BUTTON	0x0040 /* System reset via push-button dongle	*/
#define BBC_PSRC_PWRUP	0x0080 /* System reset via power-up		*/
#define BBC_PSRC_FE0	0x0100 /* CPU 0 reported Fatal_Error		*/
#define BBC_PSRC_FE1	0x0200 /* CPU 1 reported Fatal_Error		*/
#define BBC_PSRC_FE2	0x0400 /* CPU 2 reported Fatal_Error		*/
#define BBC_PSRC_FE3	0x0800 /* CPU 3 reported Fatal_Error		*/
#define BBC_PSRC_FE4	0x1000 /* Schizo reported Fatal_Error		*/
#define BBC_PSRC_FE5	0x2000 /* Safari device 5 reported Fatal_Error	*/
#define BBC_PSRC_FE6	0x4000 /* CPMS reported Fatal_Error		*/
#define BBC_PSRC_SYNTH	0x8000 /* System reset when on-board clock synthesizers
				* were updated.
				*/
#define BBC_PSRC_WDT   0x10000 /* System reset via Super I/O watchdog	*/
#define BBC_PSRC_RSC   0x20000 /* System reset via RSC remote monitoring
				* device
				*/

/* XIR Source register.  The source of an XIR event sent to a processor may
 * be determined via this register.
 */
#define BBC_XSRC_SXG0	0x01	/* CPU 0 received XIR via Soft_XIR_GEN reg */
#define BBC_XSRC_SXG1	0x02	/* CPU 1 received XIR via Soft_XIR_GEN reg */
#define BBC_XSRC_SXG2	0x04	/* CPU 2 received XIR via Soft_XIR_GEN reg */
#define BBC_XSRC_SXG3	0x08	/* CPU 3 received XIR via Soft_XIR_GEN reg */
#define BBC_XSRC_JTAG	0x10	/* All CPUs received XIR via JTAG+         */
#define BBC_XSRC_W_OR_B	0x20	/* All CPUs received XIR either because:
				 * a) Super I/O watchdog fired, or
				 * b) XIR push button was activated
				 */
#define BBC_XSRC_RESV	0xc0	/* Reserved				   */

/* Clock Synthesizers Control register.  This register provides the big-bang
 * programming interface to the two clock synthesizers of the machine.
 */
#define BBC_CSC_SLOAD	0x01	/* Directly connected to S_LOAD pins	*/
#define BBC_CSC_SDATA	0x02	/* Directly connected to S_DATA pins	*/
#define BBC_CSC_SCLOCK	0x04	/* Directly connected to S_CLOCK pins	*/
#define BBC_CSC_RESV	0x78	/* Reserved				*/
#define BBC_CSC_RST	0x80	/* Generate system reset when S_LOAD==1	*/

/* Energy Star Control register.  This register is used to generate the
 * clock frequency change trigger to the main system devices (Schizo and
 * the processors).  The transition occurs when bits in this register
 * go from 0 to 1, only one bit must be set at once else no action
 * occurs.  Basically the sequence of events is:
 * a) Choose new frequency: full, 1/2 or 1/32
 * b) Program this desired frequency into the cpus and Schizo.
 * c) Set the same value in this register.
 * d) 16 system clocks later, clear this register.
 */
#define BBC_ES_CTRL_1_1		0x01	/* Full frequency	*/
#define BBC_ES_CTRL_1_2		0x02	/* 1/2 frequency	*/
#define BBC_ES_CTRL_1_32	0x20	/* 1/32 frequency	*/
#define BBC_ES_RESV		0xdc	/* Reserved		*/

/* Energy Star Assert Change Time register.  This determines the number
 * of BBC clock cycles (which is half the system frequency) between
 * the detection of FREEZE_ACK being asserted and the assertion of
 * the CLK_CHANGE_L[2:0] signals.
 */
#define BBC_ES_ACT_VAL	0xff

/* Energy Star Assert Bypass Time register.  This determines the number
 * of BBC clock cycles (which is half the system frequency) between
 * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
 * the ESTAR_PLL_BYPASS signal.
 */
#define BBC_ES_ABT_VAL	0xffff

/* Energy Star PLL Settle Time register.  This determines the number of
 * BBC clock cycles (which is half the system frequency) between the
 * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
 * signal.
 */
#define BBC_ES_PST_VAL	0xffffffff

/* Energy Star Frequency Switch Latency register.  This is the number of
 * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
 * edge of the Safari clock at the new frequency.
 */
#define BBC_ES_FSL_VAL	0xffffffff

/* Keyboard Beep control register.  This is a simple enabler for the audio
 * beep sound.
 */
#define BBC_KBD_BEEP_ENABLE	0x01 /* Enable beep	*/
#define BBC_KBD_BEEP_RESV	0xfe /* Reserved	*/

/* Keyboard Beep Counter register.  There is a free-running counter inside
 * the BBC which runs at half the system clock.  The bit set in this register
 * determines when the audio sound is generated.  So for example if bit
 * 10 is set, the audio beep will oscillate at 1/(2**12).  The keyboard beep
 * generator automatically selects a different bit to use if the system clock
 * is changed via Energy Star.
 */
#define BBC_KBD_BCNT_BITS	0x0007fc00
#define BBC_KBC_BCNT_RESV	0xfff803ff

#endif /* _SPARC64_BBC_H */

cmd: