FM / asm

/usr/src/linux-headers-5.15.0-181/arch/xtensa/include/asm/

/usr/src/linux-headers-5.15.0-181/arch/xtensa/include/asm

Name	Size	Mode	Actions
asm-offsets.h	35	0644	edit dl rm
asm-uaccess.h	4180	0644	edit dl rm
asmmacro.h	4763	0644	edit dl rm
atomic.h	7301	0644	edit dl rm
barrier.h	594	0644	edit dl rm
bitops.h	5398	0644	edit dl rm
bootparam.h	1402	0644	edit dl rm
cache.h	1114	0644	edit dl rm
cacheasm.h	3856	0644	edit dl rm
cacheflush.h	5968	0644	edit dl rm
checksum.h	5893	0644	edit dl rm
cmpxchg.h	5684	0644	edit dl rm
coprocessor.h	4623	0644	edit dl rm
core.h	830	0644	edit dl rm
current.h	679	0644	edit dl rm
delay.h	1668	0644	edit dl rm
dma.h	1830	0644	edit dl rm
elf.h	5115	0644	edit dl rm
fixmap.h	1106	0644	edit dl rm
flat.h	440	0644	edit dl rm
ftrace.h	979	0644	edit dl rm
futex.h	3889	0644	edit dl rm
highmem.h	2167	0644	edit dl rm
hw_breakpoint.h	1597	0644	edit dl rm
initialize_mmu.h	5196	0644	edit dl rm
io.h	1959	0644	edit dl rm
irq.h	1127	0644	edit dl rm
irqflags.h	2069	0644	edit dl rm
jump_label.h	1655	0644	edit dl rm
kasan.h	859	0644	edit dl rm
Kbuild	230	0644	edit dl rm
kmem_layout.h	2790	0644	edit dl rm
linkage.h	154	0644	edit dl rm
mmu.h	462	0644	edit dl rm
mmu_context.h	3624	0644	edit dl rm
mxregs.h	1330	0644	edit dl rm
nommu_context.h	156	0644	edit dl rm
page.h	5793	0644	edit dl rm
pci-bridge.h	2170	0644	edit dl rm
pci.h	1302	0644	edit dl rm
perf_event.h	108	0644	edit dl rm
pgalloc.h	1405	0644	edit dl rm
pgtable.h	14470	0644	edit dl rm
platform.h	1528	0644	edit dl rm
processor.h	7705	0644	edit dl rm
ptrace.h	3321	0644	edit dl rm
regs.h	4017	0644	edit dl rm
seccomp.h	287	0644	edit dl rm
serial.h	443	0644	edit dl rm
shmparam.h	561	0644	edit dl rm
signal.h	502	0644	edit dl rm
smp.h	967	0644	edit dl rm
spinlock.h	472	0644	edit dl rm
spinlock_types.h	317	0644	edit dl rm
stackprotector.h	1140	0644	edit dl rm
stacktrace.h	1158	0644	edit dl rm
string.h	3385	0644	edit dl rm
switch_to.h	601	0644	edit dl rm
syscall.h	2140	0644	edit dl rm
sysmem.h	426	0644	edit dl rm
thread_info.h	3965	0644	edit dl rm
timex.h	1440	0644	edit dl rm
tlb.h	475	0644	edit dl rm
tlbflush.h	5620	0644	edit dl rm
traps.h	2779	0644	edit dl rm
uaccess.h	9375	0644	edit dl rm
ucontext.h	540	0644	edit dl rm
unistd.h	370	0644	edit dl rm
vectors.h	3276	0644	edit dl rm
vermagic.h	433	0644	edit dl rm
vmalloc.h	96	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/arch/xtensa/include/asm/cacheflush.h (5968B)

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * (C) 2001 - 2013 Tensilica Inc.
 */

#ifndef _XTENSA_CACHEFLUSH_H
#define _XTENSA_CACHEFLUSH_H

#include <linux/mm.h>
#include <asm/processor.h>
#include <asm/page.h>

/*
 * Lo-level routines for cache flushing.
 *
 * invalidate data or instruction cache:
 *
 * __invalidate_icache_all()
 * __invalidate_icache_page(adr)
 * __invalidate_dcache_page(adr)
 * __invalidate_icache_range(from,size)
 * __invalidate_dcache_range(from,size)
 *
 * flush data cache:
 *
 * __flush_dcache_page(adr)
 *
 * flush and invalidate data cache:
 *
 * __flush_invalidate_dcache_all()
 * __flush_invalidate_dcache_page(adr)
 * __flush_invalidate_dcache_range(from,size)
 *
 * specials for cache aliasing:
 *
 * __flush_invalidate_dcache_page_alias(vaddr,paddr)
 * __invalidate_dcache_page_alias(vaddr,paddr)
 * __invalidate_icache_page_alias(vaddr,paddr)
 */

extern void __invalidate_dcache_all(void);
extern void __invalidate_icache_all(void);
extern void __invalidate_dcache_page(unsigned long);
extern void __invalidate_icache_page(unsigned long);
extern void __invalidate_icache_range(unsigned long, unsigned long);
extern void __invalidate_dcache_range(unsigned long, unsigned long);

#if XCHAL_DCACHE_IS_WRITEBACK
extern void __flush_invalidate_dcache_all(void);
extern void __flush_dcache_page(unsigned long);
extern void __flush_dcache_range(unsigned long, unsigned long);
extern void __flush_invalidate_dcache_page(unsigned long);
extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
#else
static inline void __flush_dcache_page(unsigned long va)
{
}
static inline void __flush_dcache_range(unsigned long va, unsigned long sz)
{
}
# define __flush_invalidate_dcache_all()	__invalidate_dcache_all()
# define __flush_invalidate_dcache_page(p)	__invalidate_dcache_page(p)
# define __flush_invalidate_dcache_range(p,s)	__invalidate_dcache_range(p,s)
#endif

#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
#else
static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
							unsigned long phys) { }
static inline void __invalidate_dcache_page_alias(unsigned long virt,
						  unsigned long phys) { }
#endif
#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
#else
static inline void __invalidate_icache_page_alias(unsigned long virt,
						unsigned long phys) { }
#endif

/*
 * We have physically tagged caches - nothing to do here -
 * unless we have cache aliasing.
 *
 * Pages can get remapped. Because this might change the 'color' of that page,
 * we have to flush the cache before the PTE is changed.
 * (see also Documentation/core-api/cachetlb.rst)
 */

#if defined(CONFIG_MMU) && \
	((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))

#ifdef CONFIG_SMP
void flush_cache_all(void);
void flush_cache_range(struct vm_area_struct*, ulong, ulong);
void flush_icache_range(unsigned long start, unsigned long end);
void flush_cache_page(struct vm_area_struct*,
			     unsigned long, unsigned long);
#else
#define flush_cache_all local_flush_cache_all
#define flush_cache_range local_flush_cache_range
#define flush_icache_range local_flush_icache_range
#define flush_cache_page  local_flush_cache_page
#endif

#define local_flush_cache_all()						\
	do {								\
		__flush_invalidate_dcache_all();			\
		__invalidate_icache_all();				\
	} while (0)

#define flush_cache_mm(mm)		flush_cache_all()
#define flush_cache_dup_mm(mm)		flush_cache_mm(mm)

#define flush_cache_vmap(start,end)	flush_cache_all()
#define flush_cache_vunmap(start,end)	flush_cache_all()

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
extern void flush_dcache_page(struct page*);

void local_flush_cache_range(struct vm_area_struct *vma,
		unsigned long start, unsigned long end);
void local_flush_cache_page(struct vm_area_struct *vma,
		unsigned long address, unsigned long pfn);

#else

#define flush_cache_all()				do { } while (0)
#define flush_cache_mm(mm)				do { } while (0)
#define flush_cache_dup_mm(mm)				do { } while (0)

#define flush_cache_vmap(start,end)			do { } while (0)
#define flush_cache_vunmap(start,end)			do { } while (0)

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page)				do { } while (0)

#define flush_icache_range local_flush_icache_range
#define flush_cache_page(vma, addr, pfn)		do { } while (0)
#define flush_cache_range(vma, start, end)		do { } while (0)

#endif

#define flush_icache_user_range flush_icache_range

/* Ensure consistency between data and instruction cache. */
#define local_flush_icache_range(start, end)				\
	do {								\
		__flush_dcache_range(start, (end) - (start));		\
		__invalidate_icache_range(start,(end) - (start));	\
	} while (0)

/* This is not required, see Documentation/core-api/cachetlb.rst */
#define	flush_icache_page(vma,page)			do { } while (0)

#define flush_dcache_mmap_lock(mapping)			do { } while (0)
#define flush_dcache_mmap_unlock(mapping)		do { } while (0)

#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)

extern void copy_to_user_page(struct vm_area_struct*, struct page*,
		unsigned long, void*, const void*, unsigned long);
extern void copy_from_user_page(struct vm_area_struct*, struct page*,
		unsigned long, void*, const void*, unsigned long);

#else

#define copy_to_user_page(vma, page, vaddr, dst, src, len)		\
	do {								\
		memcpy(dst, src, len);					\
		__flush_dcache_range((unsigned long) dst, len);		\
		__invalidate_icache_range((unsigned long) dst, len);	\
	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy(dst, src, len)

#endif

#endif /* _XTENSA_CACHEFLUSH_H */

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