FM / nand

/usr/src/linux-headers-5.15.0-181/drivers/mtd/nand/

/usr/src/linux-headers-5.15.0-181/drivers/mtd/nand

Name	Size	Mode	Actions
onenand/	-	0755	rm
raw/	-	0755	rm
spi/	-	0755	rm
Kconfig	1347	0644	edit dl rm
Makefile	315	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/drivers/mtd/nand/Kconfig (1347B)

# SPDX-License-Identifier: GPL-2.0-only

menu "NAND"

config MTD_NAND_CORE
	tristate

source "drivers/mtd/nand/onenand/Kconfig"
source "drivers/mtd/nand/raw/Kconfig"
source "drivers/mtd/nand/spi/Kconfig"

menu "ECC engine support"

config MTD_NAND_ECC
       bool
       select MTD_NAND_CORE

config MTD_NAND_ECC_SW_HAMMING
	bool "Software Hamming ECC engine"
	default y if MTD_RAW_NAND
	select MTD_NAND_ECC
	help
	  This enables support for software Hamming error
	  correction. This correction can correct up to 1 bit error
	  per chunk and detect up to 2 bit errors. While it used to be
	  widely used with old parts, newer NAND chips usually require
	  more strength correction and in this case BCH or RS will be
	  preferred.

config MTD_NAND_ECC_SW_HAMMING_SMC
	bool "NAND ECC Smart Media byte order"
	depends on MTD_NAND_ECC_SW_HAMMING
	default n
	help
	  Software ECC according to the Smart Media Specification.
	  The original Linux implementation had byte 0 and 1 swapped.

config MTD_NAND_ECC_SW_BCH
	bool "Software BCH ECC engine"
	select BCH
	select MTD_NAND_ECC
	default n
	help
	  This enables support for software BCH error correction. Binary BCH
	  codes are more powerful and cpu intensive than traditional Hamming
	  ECC codes. They are used with NAND devices requiring more than 1 bit
	  of error correction.

endmenu

cmd: