FM / linux

/usr/src/linux-headers-5.15.0-181/include/linux/

/usr/src/linux-headers-5.15.0-181/include/linux

Name	Size	Mode	Actions
amba/	-	0755	rm
atomic/	-	0755	rm
avf/	-	0755	rm
bcma/	-	0755	rm
byteorder/	-	0755	rm
can/	-	0755	rm
ceph/	-	0755	rm
clk/	-	0755	rm
crush/	-	0755	rm
decompress/	-	0755	rm
device/	-	0755	rm
dma/	-	0755	rm
dsa/	-	0755	rm
extcon/	-	0755	rm
firmware/	-	0755	rm
fpga/	-	0755	rm
fsl/	-	0755	rm
gpio/	-	0755	rm
greybus/	-	0755	rm
hsi/	-	0755	rm
i3c/	-	0755	rm
iio/	-	0755	rm
input/	-	0755	rm
irqchip/	-	0755	rm
isdn/	-	0755	rm
lockd/	-	0755	rm
mailbox/	-	0755	rm
mdio/	-	0755	rm
mfd/	-	0755	rm
mlx4/	-	0755	rm
mlx5/	-	0755	rm
mmc/	-	0755	rm
mtd/	-	0755	rm
mux/	-	0755	rm
net/	-	0755	rm
netfilter/	-	0755	rm
netfilter_arp/	-	0755	rm
netfilter_bridge/	-	0755	rm
netfilter_ipv4/	-	0755	rm
netfilter_ipv6/	-	0755	rm
pcs/	-	0755	rm
perf/	-	0755	rm
phy/	-	0755	rm
pinctrl/	-	0755	rm
platform_data/	-	0755	rm
power/	-	0755	rm
qed/	-	0755	rm
raid/	-	0755	rm
regulator/	-	0755	rm
remoteproc/	-	0755	rm
reset/	-	0755	rm
rpmsg/	-	0755	rm
rtc/	-	0755	rm
sched/	-	0755	rm
soc/	-	0755	rm
soundwire/	-	0755	rm
spi/	-	0755	rm
ssb/	-	0755	rm
sunrpc/	-	0755	rm
surface_aggregator/	-	0755	rm
ulpi/	-	0755	rm
unaligned/	-	0755	rm
usb/	-	0755	rm
8250_pci.h	1038	0644	edit dl rm
a.out.h	354	0644	edit dl rm
acct.h	2551	0644	edit dl rm
acpi.h	40902	0644	edit dl rm
acpi_dma.h	3154	0644	edit dl rm
acpi_iort.h	2403	0644	edit dl rm
acpi_mdio.h	819	0644	edit dl rm
acpi_pmtmr.h	674	0644	edit dl rm
acpi_viot.h	478	0644	edit dl rm
adb.h	1832	0644	edit dl rm
adfs_fs.h	574	0644	edit dl rm
adreno-smmu-priv.h	2807	0644	edit dl rm
adxl.h	310	0644	edit dl rm
aer.h	1822	0644	edit dl rm
agpgart.h	3881	0644	edit dl rm
agp_backend.h	3534	0644	edit dl rm
ahci-remap.h	607	0644	edit dl rm
ahci_platform.h	1747	0644	edit dl rm
aio.h	651	0644	edit dl rm
alarmtimer.h	1990	0644	edit dl rm
alcor_pci.h	9043	0644	edit dl rm
align.h	552	0644	edit dl rm
altera_jtaguart.h	379	0644	edit dl rm
altera_uart.h	397	0644	edit dl rm
amd-iommu.h	6325	0644	edit dl rm
anon_inodes.h	670	0644	edit dl rm
apm-emulation.h	1599	0644	edit dl rm
apm_bios.h	2305	0644	edit dl rm
apple-gmux.h	918	0644	edit dl rm
apple_bl.h	498	0644	edit dl rm
arch_topology.h	2551	0644	edit dl rm
arm-cci.h	1390	0644	edit dl rm
arm-smccc.h	17382	0644	edit dl rm
armada-37xx-rwtm-mailbox.h	431	0644	edit dl rm
arm_ffa.h	7545	0644	edit dl rm
arm_sdei.h	2730	0644	edit dl rm
array_size.h	332	0644	edit dl rm
ascii85.h	555	0644	edit dl rm
asn1.h	1832	0644	edit dl rm
asn1_ber_bytecode.h	2576	0644	edit dl rm
asn1_decoder.h	468	0644	edit dl rm
asn1_encoder.h	1006	0644	edit dl rm
assoc_array.h	2949	0644	edit dl rm
assoc_array_priv.h	5423	0644	edit dl rm
async.h	4439	0644	edit dl rm
async_tx.h	6860	0644	edit dl rm
ata.h	33799	0644	edit dl rm
atalk.h	4586	0644	edit dl rm
ata_platform.h	749	0644	edit dl rm
ath9k_platform.h	1477	0644	edit dl rm
atm.h	287	0644	edit dl rm
atmdev.h	10477	0644	edit dl rm
atmel-isc-media.h	2115	0644	edit dl rm
atmel-mci.h	1429	0644	edit dl rm
atmel-ssc.h	9971	0644	edit dl rm
atmel_pdc.h	1295	0644	edit dl rm
atm_tcp.h	511	0644	edit dl rm
atomic.h	2644	0644	edit dl rm
attribute_container.h	2803	0644	edit dl rm
audit.h	19921	0644	edit dl rm
auto_dev-ioctl.h	296	0644	edit dl rm
auto_fs.h	278	0644	edit dl rm
auxiliary_bus.h	2539	0644	edit dl rm
auxvec.h	304	0644	edit dl rm
average.h	2481	0644	edit dl rm
backing-dev-defs.h	8753	0644	edit dl rm
backing-dev.h	12189	0644	edit dl rm
backlight.h	13447	0644	edit dl rm
badblocks.h	2188	0644	edit dl rm
balloon_compaction.h	5892	0644	edit dl rm
bcd.h	559	0644	edit dl rm
bch.h	2152	0644	edit dl rm
bcm47xx_nvram.h	1033	0644	edit dl rm
bcm47xx_sprom.h	616	0644	edit dl rm
bcm47xx_wdt.h	555	0644	edit dl rm
bcm963xx_nvram.h	3036	0644	edit dl rm
bcm963xx_tag.h	3685	0644	edit dl rm
binfmts.h	4683	0644	edit dl rm
bio.h	20108	0644	edit dl rm
bitfield.h	5460	0644	edit dl rm
bitmap.h	22664	0644	edit dl rm
bitops.h	8733	0644	edit dl rm
bitrev.h	2594	0644	edit dl rm
bits.h	1387	0644	edit dl rm
bit_spinlock.h	2360	0644	edit dl rm
blk-cgroup.h	22648	0644	edit dl rm
blk-crypto.h	4117	0644	edit dl rm
blk-mq-pci.h	269	0644	edit dl rm
blk-mq-rdma.h	273	0644	edit dl rm
blk-mq-virtio.h	293	0644	edit dl rm
blk-mq.h	19834	0644	edit dl rm
blk-pm.h	708	0644	edit dl rm
blkdev.h	58041	0644	edit dl rm
blkpg.h	436	0644	edit dl rm
blktrace_api.h	3858	0644	edit dl rm
blk_types.h	15669	0644	edit dl rm
blockgroup_lock.h	810	0644	edit dl rm
bma150.h	1286	0644	edit dl rm
bootconfig.h	8712	0644	edit dl rm
bootmem_info.h	1733	0644	edit dl rm
bottom_half.h	974	0644	edit dl rm
bpf-cgroup.h	18796	0644	edit dl rm
bpf-netns.h	1559	0644	edit dl rm
bpf.h	76212	0644	edit dl rm
bpfilter.h	791	0644	edit dl rm
bpfptr.h	2029	0644	edit dl rm
bpf_lirc.h	698	0644	edit dl rm
bpf_local_storage.h	5359	0644	edit dl rm
bpf_lsm.h	1456	0644	edit dl rm
bpf_trace.h	166	0644	edit dl rm
bpf_types.h	5536	0644	edit dl rm
bpf_verifier.h	20865	0644	edit dl rm
brcmphy.h	13994	0644	edit dl rm
bsearch.h	624	0644	edit dl rm
bsg-lib.h	1759	0644	edit dl rm
bsg.h	492	0644	edit dl rm
btf.h	7432	0644	edit dl rm
btf_ids.h	5463	0644	edit dl rm
btree-128.h	2737	0644	edit dl rm
btree-type.h	3991	0644	edit dl rm
btree.h	7000	0644	edit dl rm
btrfs.h	145	0644	edit dl rm
buffer_head.h	14814	0644	edit dl rm
bug.h	2220	0644	edit dl rm
build-salt.h	375	0644	edit dl rm
buildid.h	561	0644	edit dl rm
build_bug.h	2823	0644	edit dl rm
bvec.h	6319	0644	edit dl rm
c2port.h	1384	0644	edit dl rm
cache.h	2616	0644	edit dl rm
cacheinfo.h	3837	0644	edit dl rm
capability.h	8486	0644	edit dl rm
cb710.h	5490	0644	edit dl rm
cciss_ioctl.h	1053	0644	edit dl rm
ccp.h	18577	0644	edit dl rm
cc_platform.h	2378	0644	edit dl rm
cdev.h	845	0644	edit dl rm
cdrom.h	9197	0644	edit dl rm
cfag12864b.h	1509	0644	edit dl rm
cfi.h	1152	0644	edit dl rm
cgroup-defs.h	24815	0644	edit dl rm
cgroup.h	28840	0644	edit dl rm
cgroup_rdma.h	1206	0644	edit dl rm
cgroup_subsys.h	1259	0644	edit dl rm
circ_buf.h	1120	0644	edit dl rm
cleancache.h	3982	0644	edit dl rm
cleanup.h	4986	0644	edit dl rm
clk-provider.h	59330	0644	edit dl rm
clk.h	34418	0644	edit dl rm
clkdev.h	1322	0644	edit dl rm
clockchips.h	7445	0644	edit dl rm
clocksource.h	10227	0644	edit dl rm
clocksource_ids.h	247	0644	edit dl rm
cm4000_cs.h	199	0644	edit dl rm
cma.h	2004	0644	edit dl rm
cnt32_to_63.h	3545	0644	edit dl rm
cn_proc.h	1890	0644	edit dl rm
coda.h	2215	0644	edit dl rm
compaction.h	7319	0644	edit dl rm
compat.h	32122	0644	edit dl rm
compiler-clang.h	4150	0644	edit dl rm
compiler-gcc.h	5021	0644	edit dl rm
compiler-intel.h	949	0644	edit dl rm
compiler-version.h	517	0644	edit dl rm
compiler.h	8553	0644	edit dl rm
compiler_attributes.h	13557	0644	edit dl rm
compiler_types.h	11023	0644	edit dl rm
completion.h	4101	0644	edit dl rm
component.h	4163	0644	edit dl rm
configfs.h	8683	0644	edit dl rm
connector.h	3927	0644	edit dl rm
console.h	7758	0644	edit dl rm
consolemap.h	1076	0644	edit dl rm
console_struct.h	7253	0644	edit dl rm
const.h	421	0644	edit dl rm
container.h	610	0644	edit dl rm
context_tracking.h	3362	0644	edit dl rm
context_tracking_state.h	1616	0644	edit dl rm
cookie.h	1254	0644	edit dl rm
cordic.h	2132	0644	edit dl rm
coredump.h	1154	0644	edit dl rm
coresight-pmu.h	1355	0644	edit dl rm
coresight-stm.h	152	0644	edit dl rm
coresight.h	18449	0644	edit dl rm
counter.h	15318	0644	edit dl rm
count_zeros.h	1453	0644	edit dl rm
cper.h	16947	0644	edit dl rm
cpu.h	8485	0644	edit dl rm
cpufeature.h	1751	0644	edit dl rm
cpufreq.h	33551	0644	edit dl rm
cpuhotplug.h	16949	0644	edit dl rm
cpuidle.h	10516	0644	edit dl rm
cpuidle_haltpoll.h	312	0644	edit dl rm
cpumask.h	30089	0644	edit dl rm
cpuset.h	8351	0644	edit dl rm
cpu_cooling.h	1901	0644	edit dl rm
cpu_pm.h	2433	0644	edit dl rm
cpu_rmap.h	1721	0644	edit dl rm
crash_core.h	3465	0644	edit dl rm
crash_dump.h	4149	0644	edit dl rm
crc-ccitt.h	609	0644	edit dl rm
crc-itu-t.h	531	0644	edit dl rm
crc-t10dif.h	453	0644	edit dl rm
crc4.h	192	0644	edit dl rm
crc7.h	316	0644	edit dl rm
crc8.h	3747	0644	edit dl rm
crc16.h	540	0644	edit dl rm
crc32.h	2894	0644	edit dl rm
crc32c.h	331	0644	edit dl rm
crc32poly.h	610	0644	edit dl rm
crc64.h	280	0644	edit dl rm
cred.h	12804	0644	edit dl rm
crypto.h	27890	0644	edit dl rm
cs5535.h	6277	0644	edit dl rm
ctype.h	1912	0644	edit dl rm
cuda.h	613	0644	edit dl rm
damon.h	10601	0644	edit dl rm
dasd_mod.h	204	0644	edit dl rm
davinci_emac.h	1080	0644	edit dl rm
dax.h	6719	0644	edit dl rm
dca.h	1922	0644	edit dl rm
dcache.h	19076	0644	edit dl rm
dccp.h	10988	0644	edit dl rm
debugfs.h	12253	0644	edit dl rm
debugobjects.h	4085	0644	edit dl rm
debug_locks.h	1627	0644	edit dl rm
delay.h	2490	0644	edit dl rm
delayacct.h	5584	0644	edit dl rm
delayed_call.h	709	0644	edit dl rm
devcoredump.h	2266	0644	edit dl rm
devfreq-event.h	6095	0644	edit dl rm
devfreq.h	14370	0644	edit dl rm
devfreq_cooling.h	2763	0644	edit dl rm
device-mapper.h	19371	0644	edit dl rm
device.h	33997	0644	edit dl rm
device_cgroup.h	1609	0644	edit dl rm
devm-helpers.h	2740	0644	edit dl rm
devpts_fs.h	1156	0644	edit dl rm
dev_printk.h	9406	0644	edit dl rm
dfl.h	2435	0644	edit dl rm
digsig.h	1212	0644	edit dl rm
dim.h	9421	0644	edit dl rm
dio.h	11019	0644	edit dl rm
dirent.h	215	0644	edit dl rm
dlm.h	6005	0644	edit dl rm
dlm_plock.h	532	0644	edit dl rm
dm-bufio.h	4992	0644	edit dl rm
dm-dirty-log.h	4038	0644	edit dl rm
dm-io.h	1980	0644	edit dl rm
dm-kcopyd.h	3013	0644	edit dl rm
dm-region-hash.h	3182	0644	edit dl rm
dm9000.h	987	0644	edit dl rm
dma-buf-map.h	8318	0644	edit dl rm
dma-buf.h	20962	0644	edit dl rm
dma-direct.h	3681	0644	edit dl rm
dma-direction.h	407	0644	edit dl rm
dma-fence-array.h	2191	0644	edit dl rm
dma-fence-chain.h	3144	0644	edit dl rm
dma-fence.h	21357	0644	edit dl rm
dma-heap.h	1616	0644	edit dl rm
dma-iommu.h	2265	0644	edit dl rm
dma-map-ops.h	13197	0644	edit dl rm
dma-mapping.h	20589	0644	edit dl rm
dma-resv.h	12236	0644	edit dl rm
dmaengine.h	54851	0644	edit dl rm
dmapool.h	1832	0644	edit dl rm
dmar.h	7929	0644	edit dl rm
dmi.h	4372	0644	edit dl rm
dnotify.h	1044	0644	edit dl rm
dns_resolver.h	1390	0644	edit dl rm
dqblk_qtree.h	2238	0644	edit dl rm
dqblk_v1.h	327	0644	edit dl rm
dqblk_v2.h	406	0644	edit dl rm
drbd.h	10311	0644	edit dl rm
drbd_genl.h	22010	0644	edit dl rm
drbd_genl_api.h	1808	0644	edit dl rm
drbd_limits.h	8003	0644	edit dl rm
ds2782_battery.h	158	0644	edit dl rm
dtlk.h	3584	0644	edit dl rm
dtpm.h	1684	0644	edit dl rm
dw_apb_timer.h	1566	0644	edit dl rm
dynamic_debug.h	6471	0644	edit dl rm
dynamic_queue_limits.h	3812	0644	edit dl rm
earlycpio.h	359	0644	edit dl rm
ecryptfs.h	3915	0644	edit dl rm
edac.h	19924	0644	edit dl rm
edd.h	1077	0644	edit dl rm
eeprom_93cx6.h	2707	0644	edit dl rm
eeprom_93xx46.h	1062	0644	edit dl rm
efi-bgrt.h	644	0644	edit dl rm
efi.h	43038	0644	edit dl rm
efi_embedded_fw.h	1060	0644	edit dl rm
efs_vh.h	1585	0644	edit dl rm
eisa.h	3031	0644	edit dl rm
elevator.h	5653	0644	edit dl rm
elf-fdpic.h	2030	0644	edit dl rm
elf-randomize.h	583	0644	edit dl rm
elf.h	3030	0644	edit dl rm
elfcore-compat.h	1302	0644	edit dl rm
elfcore.h	4209	0644	edit dl rm
elfnote-lto.h	314	0644	edit dl rm
elfnote.h	3626	0644	edit dl rm
enclosure.h	4112	0644	edit dl rm
energy_model.h	8361	0644	edit dl rm
entry-common.h	17359	0644	edit dl rm
entry-kvm.h	2800	0644	edit dl rm
err.h	1527	0644	edit dl rm
errname.h	283	0644	edit dl rm
errno.h	1481	0644	edit dl rm
error-injection.h	607	0644	edit dl rm
errqueue.h	524	0644	edit dl rm
errseq.h	382	0644	edit dl rm
etherdevice.h	17607	0644	edit dl rm
ethtool.h	32505	0644	edit dl rm
ethtool_netlink.h	2029	0644	edit dl rm
eventfd.h	2336	0644	edit dl rm
eventpoll.h	2472	0644	edit dl rm
evm.h	3500	0644	edit dl rm
export.h	5394	0644	edit dl rm
exportfs.h	8421	0644	edit dl rm
ext2_fs.h	967	0644	edit dl rm
extable.h	1309	0644	edit dl rm
extcon-provider.h	3919	0644	edit dl rm
extcon.h	10399	0644	edit dl rm
f2fs_fs.h	19471	0644	edit dl rm
f75375s.h	541	0644	edit dl rm
falloc.h	1624	0644	edit dl rm
fanotify.h	4547	0644	edit dl rm
fault-inject-usercopy.h	496	0644	edit dl rm
fault-inject.h	1975	0644	edit dl rm
fb.h	28958	0644	edit dl rm
fbcon.h	2136	0644	edit dl rm
fcdevice.h	774	0644	edit dl rm
fcntl.h	1698	0644	edit dl rm
fd.h	490	0644	edit dl rm
fddidevice.h	833	0644	edit dl rm
fdtable.h	3571	0644	edit dl rm
fec.h	463	0644	edit dl rm
fiemap.h	713	0644	edit dl rm
file.h	3158	0644	edit dl rm
fileattr.h	1952	0644	edit dl rm
filter.h	43995	0644	edit dl rm
fips.h	303	0644	edit dl rm
firewire.h	13718	0644	edit dl rm
firmware-map.h	959	0644	edit dl rm
firmware.h	3348	0644	edit dl rm
fixp-arith.h	4290	0644	edit dl rm
flat.h	2629	0644	edit dl rm
flex_proportions.h	2881	0644	edit dl rm
font.h	1714	0644	edit dl rm
fortify-string.h	9329	0644	edit dl rm
freelist.h	3890	0644	edit dl rm
freezer.h	9193	0644	edit dl rm
frontswap.h	3118	0644	edit dl rm
fs.h	125506	0644	edit dl rm
fscache-cache.h	19025	0644	edit dl rm
fscache.h	30303	0644	edit dl rm
fscrypt.h	30622	0644	edit dl rm
fsi-occ.h	681	0644	edit dl rm
fsi-sbefifo.h	629	0644	edit dl rm
fsi.h	2318	0644	edit dl rm
fsl-diu-fb.h	3963	0644	edit dl rm
fsldma.h	202	0644	edit dl rm
fsl_devices.h	4261	0644	edit dl rm
fsl_hypervisor.h	2824	0644	edit dl rm
fsl_ifc.h	25063	0644	edit dl rm
fsnotify.h	10287	0644	edit dl rm
fsnotify_backend.h	30006	0644	edit dl rm
fsverity.h	6914	0644	edit dl rm
fs_context.h	8818	0644	edit dl rm
fs_enet_pd.h	3457	0644	edit dl rm
fs_parser.h	4543	0644	edit dl rm
fs_pin.h	539	0644	edit dl rm
fs_stack.h	811	0644	edit dl rm
fs_struct.h	1066	0644	edit dl rm
fs_types.h	2071	0644	edit dl rm
fs_uart_pd.h	1523	0644	edit dl rm
ftrace.h	35597	0644	edit dl rm
ftrace_irq.h	884	0644	edit dl rm
futex.h	2497	0644	edit dl rm
fwnode.h	6989	0644	edit dl rm
fwnode_mdio.h	858	0644	edit dl rm
gameport.h	5549	0644	edit dl rm
gcd.h	193	0644	edit dl rm
genalloc.h	7912	0644	edit dl rm
generic-radix-tree.h	6504	0644	edit dl rm
genetlink.h	589	0644	edit dl rm
genhd.h	9055	0644	edit dl rm
genl_magic_func.h	11809	0644	edit dl rm
genl_magic_struct.h	7793	0644	edit dl rm
getcpu.h	641	0644	edit dl rm
gfp.h	26892	0644	edit dl rm
glob.h	256	0644	edit dl rm
gnss.h	1601	0644	edit dl rm
goldfish.h	878	0644	edit dl rm
gpio-pxa.h	571	0644	edit dl rm
gpio.h	5423	0644	edit dl rm
gpio_keys.h	1782	0644	edit dl rm
greybus.h	4240	0644	edit dl rm
hardirq.h	3516	0644	edit dl rm
hash.h	3071	0644	edit dl rm
hashtable.h	6827	0644	edit dl rm
hdlc.h	3267	0644	edit dl rm
hdlcdrv.h	6468	0644	edit dl rm
hdmi.h	12705	0644	edit dl rm
hid-debug.h	1458	0644	edit dl rm
hid-roccat.h	484	0644	edit dl rm
hid-sensor-hub.h	9190	0644	edit dl rm
hid-sensor-ids.h	7617	0644	edit dl rm
hid.h	38923	0644	edit dl rm
hidden.h	966	0644	edit dl rm
hiddev.h	1458	0644	edit dl rm
hidraw.h	1146	0644	edit dl rm
highmem-internal.h	5239	0644	edit dl rm
highmem.h	9731	0644	edit dl rm
highuid.h	3194	0644	edit dl rm
hil.h	18857	0644	edit dl rm
hil_mlc.h	5248	0644	edit dl rm
hippidevice.h	1052	0644	edit dl rm
hmm.h	4168	0644	edit dl rm
host1x.h	10993	0644	edit dl rm
hpet.h	2615	0644	edit dl rm
hp_sdc.h	14352	0644	edit dl rm
hrtimer.h	16515	0644	edit dl rm
hrtimer_defs.h	660	0644	edit dl rm
htcpld.h	617	0644	edit dl rm
hugetlb.h	30416	0644	edit dl rm
hugetlb_cgroup.h	7241	0644	edit dl rm
hugetlb_inline.h	374	0644	edit dl rm
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Edit: /usr/src/linux-headers-5.15.0-181/include/linux/fsl_ifc.h (25063B)

/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Freescale Integrated Flash Controller
 *
 * Copyright 2011 Freescale Semiconductor, Inc
 *
 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
 */

#ifndef __ASM_FSL_IFC_H
#define __ASM_FSL_IFC_H

#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>

#include <linux/of_platform.h>
#include <linux/interrupt.h>

/*
 * The actual number of banks implemented depends on the IFC version
 *    - IFC version 1.0 implements 4 banks.
 *    - IFC version 1.1 onward implements 8 banks.
 */
#define FSL_IFC_BANK_COUNT 8

#define FSL_IFC_VERSION_MASK	0x0F0F0000
#define FSL_IFC_VERSION_1_0_0	0x01000000
#define FSL_IFC_VERSION_1_1_0	0x01010000
#define FSL_IFC_VERSION_2_0_0	0x02000000

#define PGOFFSET_64K	(64*1024)
#define PGOFFSET_4K	(4*1024)

/*
 * CSPR - Chip Select Property Register
 */
#define CSPR_BA				0xFFFF0000
#define CSPR_BA_SHIFT			16
#define CSPR_PORT_SIZE			0x00000180
#define CSPR_PORT_SIZE_SHIFT		7
/* Port Size 8 bit */
#define CSPR_PORT_SIZE_8		0x00000080
/* Port Size 16 bit */
#define CSPR_PORT_SIZE_16		0x00000100
/* Port Size 32 bit */
#define CSPR_PORT_SIZE_32		0x00000180
/* Write Protect */
#define CSPR_WP				0x00000040
#define CSPR_WP_SHIFT			6
/* Machine Select */
#define CSPR_MSEL			0x00000006
#define CSPR_MSEL_SHIFT			1
/* NOR */
#define CSPR_MSEL_NOR			0x00000000
/* NAND */
#define CSPR_MSEL_NAND			0x00000002
/* GPCM */
#define CSPR_MSEL_GPCM			0x00000004
/* Bank Valid */
#define CSPR_V				0x00000001
#define CSPR_V_SHIFT			0

/*
 * Address Mask Register
 */
#define IFC_AMASK_MASK			0xFFFF0000
#define IFC_AMASK_SHIFT			16
#define IFC_AMASK(n)			(IFC_AMASK_MASK << \
					(__ilog2(n) - IFC_AMASK_SHIFT))

/*
 * Chip Select Option Register IFC_NAND Machine
 */
/* Enable ECC Encoder */
#define CSOR_NAND_ECC_ENC_EN		0x80000000
#define CSOR_NAND_ECC_MODE_MASK		0x30000000
/* 4 bit correction per 520 Byte sector */
#define CSOR_NAND_ECC_MODE_4		0x00000000
/* 8 bit correction per 528 Byte sector */
#define CSOR_NAND_ECC_MODE_8		0x10000000
/* Enable ECC Decoder */
#define CSOR_NAND_ECC_DEC_EN		0x04000000
/* Row Address Length */
#define CSOR_NAND_RAL_MASK		0x01800000
#define CSOR_NAND_RAL_SHIFT		20
#define CSOR_NAND_RAL_1			0x00000000
#define CSOR_NAND_RAL_2			0x00800000
#define CSOR_NAND_RAL_3			0x01000000
#define CSOR_NAND_RAL_4			0x01800000
/* Page Size 512b, 2k, 4k */
#define CSOR_NAND_PGS_MASK		0x00180000
#define CSOR_NAND_PGS_SHIFT		16
#define CSOR_NAND_PGS_512		0x00000000
#define CSOR_NAND_PGS_2K		0x00080000
#define CSOR_NAND_PGS_4K		0x00100000
#define CSOR_NAND_PGS_8K		0x00180000
/* Spare region Size */
#define CSOR_NAND_SPRZ_MASK		0x0000E000
#define CSOR_NAND_SPRZ_SHIFT		13
#define CSOR_NAND_SPRZ_16		0x00000000
#define CSOR_NAND_SPRZ_64		0x00002000
#define CSOR_NAND_SPRZ_128		0x00004000
#define CSOR_NAND_SPRZ_210		0x00006000
#define CSOR_NAND_SPRZ_218		0x00008000
#define CSOR_NAND_SPRZ_224		0x0000A000
#define CSOR_NAND_SPRZ_CSOR_EXT		0x0000C000
/* Pages Per Block */
#define CSOR_NAND_PB_MASK		0x00000700
#define CSOR_NAND_PB_SHIFT		8
#define CSOR_NAND_PB(n)		((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
/* Time for Read Enable High to Output High Impedance */
#define CSOR_NAND_TRHZ_MASK		0x0000001C
#define CSOR_NAND_TRHZ_SHIFT		2
#define CSOR_NAND_TRHZ_20		0x00000000
#define CSOR_NAND_TRHZ_40		0x00000004
#define CSOR_NAND_TRHZ_60		0x00000008
#define CSOR_NAND_TRHZ_80		0x0000000C
#define CSOR_NAND_TRHZ_100		0x00000010
/* Buffer control disable */
#define CSOR_NAND_BCTLD			0x00000001

/*
 * Chip Select Option Register - NOR Flash Mode
 */
/* Enable Address shift Mode */
#define CSOR_NOR_ADM_SHFT_MODE_EN	0x80000000
/* Page Read Enable from NOR device */
#define CSOR_NOR_PGRD_EN		0x10000000
/* AVD Toggle Enable during Burst Program */
#define CSOR_NOR_AVD_TGL_PGM_EN		0x01000000
/* Address Data Multiplexing Shift */
#define CSOR_NOR_ADM_MASK		0x0003E000
#define CSOR_NOR_ADM_SHIFT_SHIFT	13
#define CSOR_NOR_ADM_SHIFT(n)	((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
/* Type of the NOR device hooked */
#define CSOR_NOR_NOR_MODE_AYSNC_NOR	0x00000000
#define CSOR_NOR_NOR_MODE_AVD_NOR	0x00000020
/* Time for Read Enable High to Output High Impedance */
#define CSOR_NOR_TRHZ_MASK		0x0000001C
#define CSOR_NOR_TRHZ_SHIFT		2
#define CSOR_NOR_TRHZ_20		0x00000000
#define CSOR_NOR_TRHZ_40		0x00000004
#define CSOR_NOR_TRHZ_60		0x00000008
#define CSOR_NOR_TRHZ_80		0x0000000C
#define CSOR_NOR_TRHZ_100		0x00000010
/* Buffer control disable */
#define CSOR_NOR_BCTLD			0x00000001

/*
 * Chip Select Option Register - GPCM Mode
 */
/* GPCM Mode - Normal */
#define CSOR_GPCM_GPMODE_NORMAL		0x00000000
/* GPCM Mode - GenericASIC */
#define CSOR_GPCM_GPMODE_ASIC		0x80000000
/* Parity Mode odd/even */
#define CSOR_GPCM_PARITY_EVEN		0x40000000
/* Parity Checking enable/disable */
#define CSOR_GPCM_PAR_EN		0x20000000
/* GPCM Timeout Count */
#define CSOR_GPCM_GPTO_MASK		0x0F000000
#define CSOR_GPCM_GPTO_SHIFT		24
#define CSOR_GPCM_GPTO(n)	((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
/* GPCM External Access Termination mode for read access */
#define CSOR_GPCM_RGETA_EXT		0x00080000
/* GPCM External Access Termination mode for write access */
#define CSOR_GPCM_WGETA_EXT		0x00040000
/* Address Data Multiplexing Shift */
#define CSOR_GPCM_ADM_MASK		0x0003E000
#define CSOR_GPCM_ADM_SHIFT_SHIFT	13
#define CSOR_GPCM_ADM_SHIFT(n)	((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
/* Generic ASIC Parity error indication delay */
#define CSOR_GPCM_GAPERRD_MASK		0x00000180
#define CSOR_GPCM_GAPERRD_SHIFT		7
#define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
/* Time for Read Enable High to Output High Impedance */
#define CSOR_GPCM_TRHZ_MASK		0x0000001C
#define CSOR_GPCM_TRHZ_20		0x00000000
#define CSOR_GPCM_TRHZ_40		0x00000004
#define CSOR_GPCM_TRHZ_60		0x00000008
#define CSOR_GPCM_TRHZ_80		0x0000000C
#define CSOR_GPCM_TRHZ_100		0x00000010
/* Buffer control disable */
#define CSOR_GPCM_BCTLD			0x00000001

/*
 * Ready Busy Status Register (RB_STAT)
 */
/* CSn is READY */
#define IFC_RB_STAT_READY_CS0		0x80000000
#define IFC_RB_STAT_READY_CS1		0x40000000
#define IFC_RB_STAT_READY_CS2		0x20000000
#define IFC_RB_STAT_READY_CS3		0x10000000

/*
 * General Control Register (GCR)
 */
#define IFC_GCR_MASK			0x8000F800
/* reset all IFC hardware */
#define IFC_GCR_SOFT_RST_ALL		0x80000000
/* Turnaroud Time of external buffer */
#define IFC_GCR_TBCTL_TRN_TIME		0x0000F800
#define IFC_GCR_TBCTL_TRN_TIME_SHIFT	11

/*
 * Common Event and Error Status Register (CM_EVTER_STAT)
 */
/* Chip select error */
#define IFC_CM_EVTER_STAT_CSER		0x80000000

/*
 * Common Event and Error Enable Register (CM_EVTER_EN)
 */
/* Chip select error checking enable */
#define IFC_CM_EVTER_EN_CSEREN		0x80000000

/*
 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
 */
/* Chip select error interrupt enable */
#define IFC_CM_EVTER_INTR_EN_CSERIREN	0x80000000

/*
 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
 */
/* transaction type of error Read/Write */
#define IFC_CM_ERATTR0_ERTYP_READ	0x80000000
#define IFC_CM_ERATTR0_ERAID		0x0FF00000
#define IFC_CM_ERATTR0_ERAID_SHIFT	20
#define IFC_CM_ERATTR0_ESRCID		0x0000FF00
#define IFC_CM_ERATTR0_ESRCID_SHIFT	8

/*
 * Clock Control Register (CCR)
 */
#define IFC_CCR_MASK			0x0F0F8800
/* Clock division ratio */
#define IFC_CCR_CLK_DIV_MASK		0x0F000000
#define IFC_CCR_CLK_DIV_SHIFT		24
#define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
/* IFC Clock Delay */
#define IFC_CCR_CLK_DLY_MASK		0x000F0000
#define IFC_CCR_CLK_DLY_SHIFT		16
#define IFC_CCR_CLK_DLY(n)		((n) << IFC_CCR_CLK_DLY_SHIFT)
/* Invert IFC clock before sending out */
#define IFC_CCR_INV_CLK_EN		0x00008000
/* Fedback IFC Clock */
#define IFC_CCR_FB_IFC_CLK_SEL		0x00000800

/*
 * Clock Status Register (CSR)
 */
/* Clk is stable */
#define IFC_CSR_CLK_STAT_STABLE		0x80000000

/*
 * IFC_NAND Machine Specific Registers
 */
/*
 * NAND Configuration Register (NCFGR)
 */
/* Auto Boot Mode */
#define IFC_NAND_NCFGR_BOOT		0x80000000
/* SRAM Initialization */
#define IFC_NAND_NCFGR_SRAM_INIT_EN	0x20000000
/* Addressing Mode-ROW0+n/COL0 */
#define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
/* Addressing Mode-ROW0+n/COL0+n */
#define IFC_NAND_NCFGR_ADDR_MODE_RC1	0x00400000
/* Number of loop iterations of FIR sequences for multi page operations */
#define IFC_NAND_NCFGR_NUM_LOOP_MASK	0x0000F000
#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT	12
#define IFC_NAND_NCFGR_NUM_LOOP(n)	((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
/* Number of wait cycles */
#define IFC_NAND_NCFGR_NUM_WAIT_MASK	0x000000FF
#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT	0

/*
 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
 */
/* General purpose FCM flash command bytes CMD0-CMD7 */
#define IFC_NAND_FCR0_CMD0		0xFF000000
#define IFC_NAND_FCR0_CMD0_SHIFT	24
#define IFC_NAND_FCR0_CMD1		0x00FF0000
#define IFC_NAND_FCR0_CMD1_SHIFT	16
#define IFC_NAND_FCR0_CMD2		0x0000FF00
#define IFC_NAND_FCR0_CMD2_SHIFT	8
#define IFC_NAND_FCR0_CMD3		0x000000FF
#define IFC_NAND_FCR0_CMD3_SHIFT	0
#define IFC_NAND_FCR1_CMD4		0xFF000000
#define IFC_NAND_FCR1_CMD4_SHIFT	24
#define IFC_NAND_FCR1_CMD5		0x00FF0000
#define IFC_NAND_FCR1_CMD5_SHIFT	16
#define IFC_NAND_FCR1_CMD6		0x0000FF00
#define IFC_NAND_FCR1_CMD6_SHIFT	8
#define IFC_NAND_FCR1_CMD7		0x000000FF
#define IFC_NAND_FCR1_CMD7_SHIFT	0

/*
 * Flash ROW and COL Address Register (ROWn, COLn)
 */
/* Main/spare region locator */
#define IFC_NAND_COL_MS			0x80000000
/* Column Address */
#define IFC_NAND_COL_CA_MASK		0x00000FFF

/*
 * NAND Flash Byte Count Register (NAND_BC)
 */
/* Byte Count for read/Write */
#define IFC_NAND_BC			0x000001FF

/*
 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
 */
/* NAND Machine specific opcodes OP0-OP14*/
#define IFC_NAND_FIR0_OP0		0xFC000000
#define IFC_NAND_FIR0_OP0_SHIFT		26
#define IFC_NAND_FIR0_OP1		0x03F00000
#define IFC_NAND_FIR0_OP1_SHIFT		20
#define IFC_NAND_FIR0_OP2		0x000FC000
#define IFC_NAND_FIR0_OP2_SHIFT		14
#define IFC_NAND_FIR0_OP3		0x00003F00
#define IFC_NAND_FIR0_OP3_SHIFT		8
#define IFC_NAND_FIR0_OP4		0x000000FC
#define IFC_NAND_FIR0_OP4_SHIFT		2
#define IFC_NAND_FIR1_OP5		0xFC000000
#define IFC_NAND_FIR1_OP5_SHIFT		26
#define IFC_NAND_FIR1_OP6		0x03F00000
#define IFC_NAND_FIR1_OP6_SHIFT		20
#define IFC_NAND_FIR1_OP7		0x000FC000
#define IFC_NAND_FIR1_OP7_SHIFT		14
#define IFC_NAND_FIR1_OP8		0x00003F00
#define IFC_NAND_FIR1_OP8_SHIFT		8
#define IFC_NAND_FIR1_OP9		0x000000FC
#define IFC_NAND_FIR1_OP9_SHIFT		2
#define IFC_NAND_FIR2_OP10		0xFC000000
#define IFC_NAND_FIR2_OP10_SHIFT	26
#define IFC_NAND_FIR2_OP11		0x03F00000
#define IFC_NAND_FIR2_OP11_SHIFT	20
#define IFC_NAND_FIR2_OP12		0x000FC000
#define IFC_NAND_FIR2_OP12_SHIFT	14
#define IFC_NAND_FIR2_OP13		0x00003F00
#define IFC_NAND_FIR2_OP13_SHIFT	8
#define IFC_NAND_FIR2_OP14		0x000000FC
#define IFC_NAND_FIR2_OP14_SHIFT	2

/*
 * Instruction opcodes to be programmed
 * in FIR registers- 6bits
 */
enum ifc_nand_fir_opcodes {
	IFC_FIR_OP_NOP,
	IFC_FIR_OP_CA0,
	IFC_FIR_OP_CA1,
	IFC_FIR_OP_CA2,
	IFC_FIR_OP_CA3,
	IFC_FIR_OP_RA0,
	IFC_FIR_OP_RA1,
	IFC_FIR_OP_RA2,
	IFC_FIR_OP_RA3,
	IFC_FIR_OP_CMD0,
	IFC_FIR_OP_CMD1,
	IFC_FIR_OP_CMD2,
	IFC_FIR_OP_CMD3,
	IFC_FIR_OP_CMD4,
	IFC_FIR_OP_CMD5,
	IFC_FIR_OP_CMD6,
	IFC_FIR_OP_CMD7,
	IFC_FIR_OP_CW0,
	IFC_FIR_OP_CW1,
	IFC_FIR_OP_CW2,
	IFC_FIR_OP_CW3,
	IFC_FIR_OP_CW4,
	IFC_FIR_OP_CW5,
	IFC_FIR_OP_CW6,
	IFC_FIR_OP_CW7,
	IFC_FIR_OP_WBCD,
	IFC_FIR_OP_RBCD,
	IFC_FIR_OP_BTRD,
	IFC_FIR_OP_RDSTAT,
	IFC_FIR_OP_NWAIT,
	IFC_FIR_OP_WFR,
	IFC_FIR_OP_SBRD,
	IFC_FIR_OP_UA,
	IFC_FIR_OP_RB,
};

/*
 * NAND Chip Select Register (NAND_CSEL)
 */
#define IFC_NAND_CSEL			0x0C000000
#define IFC_NAND_CSEL_SHIFT		26
#define IFC_NAND_CSEL_CS0		0x00000000
#define IFC_NAND_CSEL_CS1		0x04000000
#define IFC_NAND_CSEL_CS2		0x08000000
#define IFC_NAND_CSEL_CS3		0x0C000000

/*
 * NAND Operation Sequence Start (NANDSEQ_STRT)
 */
/* NAND Flash Operation Start */
#define IFC_NAND_SEQ_STRT_FIR_STRT	0x80000000
/* Automatic Erase */
#define IFC_NAND_SEQ_STRT_AUTO_ERS	0x00800000
/* Automatic Program */
#define IFC_NAND_SEQ_STRT_AUTO_PGM	0x00100000
/* Automatic Copyback */
#define IFC_NAND_SEQ_STRT_AUTO_CPB	0x00020000
/* Automatic Read Operation */
#define IFC_NAND_SEQ_STRT_AUTO_RD	0x00004000
/* Automatic Status Read */
#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD	0x00000800

/*
 * NAND Event and Error Status Register (NAND_EVTER_STAT)
 */
/* Operation Complete */
#define IFC_NAND_EVTER_STAT_OPC		0x80000000
/* Flash Timeout Error */
#define IFC_NAND_EVTER_STAT_FTOER	0x08000000
/* Write Protect Error */
#define IFC_NAND_EVTER_STAT_WPER	0x04000000
/* ECC Error */
#define IFC_NAND_EVTER_STAT_ECCER	0x02000000
/* RCW Load Done */
#define IFC_NAND_EVTER_STAT_RCW_DN	0x00008000
/* Boot Loadr Done */
#define IFC_NAND_EVTER_STAT_BOOT_DN	0x00004000
/* Bad Block Indicator search select */
#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE	0x00000800

/*
 * NAND Flash Page Read Completion Event Status Register
 * (PGRDCMPL_EVT_STAT)
 */
#define PGRDCMPL_EVT_STAT_MASK		0xFFFF0000
/* Small Page 0-15 Done */
#define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
/* Large Page(2K) 0-3 Done */
#define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
/* Large Page(4K) 0-1 Done */
#define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))

/*
 * NAND Event and Error Enable Register (NAND_EVTER_EN)
 */
/* Operation complete event enable */
#define IFC_NAND_EVTER_EN_OPC_EN	0x80000000
/* Page read complete event enable */
#define IFC_NAND_EVTER_EN_PGRDCMPL_EN	0x20000000
/* Flash Timeout error enable */
#define IFC_NAND_EVTER_EN_FTOER_EN	0x08000000
/* Write Protect error enable */
#define IFC_NAND_EVTER_EN_WPER_EN	0x04000000
/* ECC error logging enable */
#define IFC_NAND_EVTER_EN_ECCER_EN	0x02000000

/*
 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
 */
/* Enable interrupt for operation complete */
#define IFC_NAND_EVTER_INTR_OPCIR_EN		0x80000000
/* Enable interrupt for Page read complete */
#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN	0x20000000
/* Enable interrupt for Flash timeout error */
#define IFC_NAND_EVTER_INTR_FTOERIR_EN		0x08000000
/* Enable interrupt for Write protect error */
#define IFC_NAND_EVTER_INTR_WPERIR_EN		0x04000000
/* Enable interrupt for ECC error*/
#define IFC_NAND_EVTER_INTR_ECCERIR_EN		0x02000000

/*
 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
 */
#define IFC_NAND_ERATTR0_MASK		0x0C080000
/* Error on CS0-3 for NAND */
#define IFC_NAND_ERATTR0_ERCS_CS0	0x00000000
#define IFC_NAND_ERATTR0_ERCS_CS1	0x04000000
#define IFC_NAND_ERATTR0_ERCS_CS2	0x08000000
#define IFC_NAND_ERATTR0_ERCS_CS3	0x0C000000
/* Transaction type of error Read/Write */
#define IFC_NAND_ERATTR0_ERTTYPE_READ	0x00080000

/*
 * NAND Flash Status Register (NAND_FSR)
 */
/* First byte of data read from read status op */
#define IFC_NAND_NFSR_RS0		0xFF000000
/* Second byte of data read from read status op */
#define IFC_NAND_NFSR_RS1		0x00FF0000

/*
 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
 */
/* Number of ECC errors on sector n (n = 0-15) */
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK	0x0F000000
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT	24
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK	0x000F0000
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT	16
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK	0x00000F00
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT	8
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK	0x0000000F
#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT	0
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK	0x0F000000
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT	24
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK	0x000F0000
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT	16
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK	0x00000F00
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT	8
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK	0x0000000F
#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT	0
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK	0x0F000000
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT	24
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK	0x000F0000
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT	16
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK	0x00000F00
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT	8
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK	0x0000000F
#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT	0
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK	0x0F000000
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT	24
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK	0x000F0000
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT	16
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK	0x00000F00
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT	8
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK	0x0000000F
#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT	0

/*
 * NAND Control Register (NANDCR)
 */
#define IFC_NAND_NCR_FTOCNT_MASK	0x1E000000
#define IFC_NAND_NCR_FTOCNT_SHIFT	25
#define IFC_NAND_NCR_FTOCNT(n)	((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)

/*
 * NAND_AUTOBOOT_TRGR
 */
/* Trigger RCW load */
#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD	0x80000000
/* Trigget Auto Boot */
#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD	0x20000000

/*
 * NAND_MDR
 */
/* 1st read data byte when opcode SBRD */
#define IFC_NAND_MDR_RDATA0		0xFF000000
/* 2nd read data byte when opcode SBRD */
#define IFC_NAND_MDR_RDATA1		0x00FF0000

/*
 * NOR Machine Specific Registers
 */
/*
 * NOR Event and Error Status Register (NOR_EVTER_STAT)
 */
/* NOR Command Sequence Operation Complete */
#define IFC_NOR_EVTER_STAT_OPC_NOR	0x80000000
/* Write Protect Error */
#define IFC_NOR_EVTER_STAT_WPER		0x04000000
/* Command Sequence Timeout Error */
#define IFC_NOR_EVTER_STAT_STOER	0x01000000

/*
 * NOR Event and Error Enable Register (NOR_EVTER_EN)
 */
/* NOR Command Seq complete event enable */
#define IFC_NOR_EVTER_EN_OPCEN_NOR	0x80000000
/* Write Protect Error Checking Enable */
#define IFC_NOR_EVTER_EN_WPEREN		0x04000000
/* Timeout Error Enable */
#define IFC_NOR_EVTER_EN_STOEREN	0x01000000

/*
 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
 */
/* Enable interrupt for OPC complete */
#define IFC_NOR_EVTER_INTR_OPCEN_NOR	0x80000000
/* Enable interrupt for write protect error */
#define IFC_NOR_EVTER_INTR_WPEREN	0x04000000
/* Enable interrupt for timeout error */
#define IFC_NOR_EVTER_INTR_STOEREN	0x01000000

/*
 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
 */
/* Source ID for error transaction */
#define IFC_NOR_ERATTR0_ERSRCID		0xFF000000
/* AXI ID for error transation */
#define IFC_NOR_ERATTR0_ERAID		0x000FF000
/* Chip select corresponds to NOR error */
#define IFC_NOR_ERATTR0_ERCS_CS0	0x00000000
#define IFC_NOR_ERATTR0_ERCS_CS1	0x00000010
#define IFC_NOR_ERATTR0_ERCS_CS2	0x00000020
#define IFC_NOR_ERATTR0_ERCS_CS3	0x00000030
/* Type of transaction read/write */
#define IFC_NOR_ERATTR0_ERTYPE_READ	0x00000001

/*
 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
 */
#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP	0x000F0000
#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER	0x00000F00

/*
 * NOR Control Register (NORCR)
 */
#define IFC_NORCR_MASK			0x0F0F0000
/* No. of Address/Data Phase */
#define IFC_NORCR_NUM_PHASE_MASK	0x0F000000
#define IFC_NORCR_NUM_PHASE_SHIFT	24
#define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
/* Sequence Timeout Count */
#define IFC_NORCR_STOCNT_MASK		0x000F0000
#define IFC_NORCR_STOCNT_SHIFT		16
#define IFC_NORCR_STOCNT(n)	((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)

/*
 * GPCM Machine specific registers
 */
/*
 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
 */
/* Timeout error */
#define IFC_GPCM_EVTER_STAT_TOER	0x04000000
/* Parity error */
#define IFC_GPCM_EVTER_STAT_PER		0x01000000

/*
 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
 */
/* Timeout error enable */
#define IFC_GPCM_EVTER_EN_TOER_EN	0x04000000
/* Parity error enable */
#define IFC_GPCM_EVTER_EN_PER_EN	0x01000000

/*
 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
 */
/* Enable Interrupt for timeout error */
#define IFC_GPCM_EEIER_TOERIR_EN	0x04000000
/* Enable Interrupt for Parity error */
#define IFC_GPCM_EEIER_PERIR_EN		0x01000000

/*
 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
 */
/* Source ID for error transaction */
#define IFC_GPCM_ERATTR0_ERSRCID	0xFF000000
/* AXI ID for error transaction */
#define IFC_GPCM_ERATTR0_ERAID		0x000FF000
/* Chip select corresponds to GPCM error */
#define IFC_GPCM_ERATTR0_ERCS_CS0	0x00000000
#define IFC_GPCM_ERATTR0_ERCS_CS1	0x00000040
#define IFC_GPCM_ERATTR0_ERCS_CS2	0x00000080
#define IFC_GPCM_ERATTR0_ERCS_CS3	0x000000C0
/* Type of transaction read/Write */
#define IFC_GPCM_ERATTR0_ERTYPE_READ	0x00000001

/*
 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
 */
/* On which beat of address/data parity error is observed */
#define IFC_GPCM_ERATTR2_PERR_BEAT		0x00000C00
/* Parity Error on byte */
#define IFC_GPCM_ERATTR2_PERR_BYTE		0x000000F0
/* Parity Error reported in addr or data phase */
#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE	0x00000001

/*
 * GPCM Status Register (GPCM_STAT)
 */
#define IFC_GPCM_STAT_BSY		0x80000000  /* GPCM is busy */

/*
 * IFC Controller NAND Machine registers
 */
struct fsl_ifc_nand {
	__be32 ncfgr;
	u32 res1[0x4];
	__be32 nand_fcr0;
	__be32 nand_fcr1;
	u32 res2[0x8];
	__be32 row0;
	u32 res3;
	__be32 col0;
	u32 res4;
	__be32 row1;
	u32 res5;
	__be32 col1;
	u32 res6;
	__be32 row2;
	u32 res7;
	__be32 col2;
	u32 res8;
	__be32 row3;
	u32 res9;
	__be32 col3;
	u32 res10[0x24];
	__be32 nand_fbcr;
	u32 res11;
	__be32 nand_fir0;
	__be32 nand_fir1;
	__be32 nand_fir2;
	u32 res12[0x10];
	__be32 nand_csel;
	u32 res13;
	__be32 nandseq_strt;
	u32 res14;
	__be32 nand_evter_stat;
	u32 res15;
	__be32 pgrdcmpl_evt_stat;
	u32 res16[0x2];
	__be32 nand_evter_en;
	u32 res17[0x2];
	__be32 nand_evter_intr_en;
	__be32 nand_vol_addr_stat;
	u32 res18;
	__be32 nand_erattr0;
	__be32 nand_erattr1;
	u32 res19[0x10];
	__be32 nand_fsr;
	u32 res20;
	__be32 nand_eccstat[8];
	u32 res21[0x1c];
	__be32 nanndcr;
	u32 res22[0x2];
	__be32 nand_autoboot_trgr;
	u32 res23;
	__be32 nand_mdr;
	u32 res24[0x1C];
	__be32 nand_dll_lowcfg0;
	__be32 nand_dll_lowcfg1;
	u32 res25;
	__be32 nand_dll_lowstat;
	u32 res26[0x3c];
};

/*
 * IFC controller NOR Machine registers
 */
struct fsl_ifc_nor {
	__be32 nor_evter_stat;
	u32 res1[0x2];
	__be32 nor_evter_en;
	u32 res2[0x2];
	__be32 nor_evter_intr_en;
	u32 res3[0x2];
	__be32 nor_erattr0;
	__be32 nor_erattr1;
	__be32 nor_erattr2;
	u32 res4[0x4];
	__be32 norcr;
	u32 res5[0xEF];
};

/*
 * IFC controller GPCM Machine registers
 */
struct fsl_ifc_gpcm {
	__be32 gpcm_evter_stat;
	u32 res1[0x2];
	__be32 gpcm_evter_en;
	u32 res2[0x2];
	__be32 gpcm_evter_intr_en;
	u32 res3[0x2];
	__be32 gpcm_erattr0;
	__be32 gpcm_erattr1;
	__be32 gpcm_erattr2;
	__be32 gpcm_stat;
};

/*
 * IFC Controller Registers
 */
struct fsl_ifc_global {
	__be32 ifc_rev;
	u32 res1[0x2];
	struct {
		__be32 cspr_ext;
		__be32 cspr;
		u32 res2;
	} cspr_cs[FSL_IFC_BANK_COUNT];
	u32 res3[0xd];
	struct {
		__be32 amask;
		u32 res4[0x2];
	} amask_cs[FSL_IFC_BANK_COUNT];
	u32 res5[0xc];
	struct {
		__be32 csor;
		__be32 csor_ext;
		u32 res6;
	} csor_cs[FSL_IFC_BANK_COUNT];
	u32 res7[0xc];
	struct {
		__be32 ftim[4];
		u32 res8[0x8];
	} ftim_cs[FSL_IFC_BANK_COUNT];
	u32 res9[0x30];
	__be32 rb_stat;
	__be32 rb_map;
	__be32 wb_map;
	__be32 ifc_gcr;
	u32 res10[0x2];
	__be32 cm_evter_stat;
	u32 res11[0x2];
	__be32 cm_evter_en;
	u32 res12[0x2];
	__be32 cm_evter_intr_en;
	u32 res13[0x2];
	__be32 cm_erattr0;
	__be32 cm_erattr1;
	u32 res14[0x2];
	__be32 ifc_ccr;
	__be32 ifc_csr;
	__be32 ddr_ccr_low;
};

struct fsl_ifc_runtime {
	struct fsl_ifc_nand ifc_nand;
	struct fsl_ifc_nor ifc_nor;
	struct fsl_ifc_gpcm ifc_gpcm;
};

extern unsigned int convert_ifc_address(phys_addr_t addr_base);
extern int fsl_ifc_find(phys_addr_t addr_base);

/* overview of the fsl ifc controller */

struct fsl_ifc_ctrl {
	/* device info */
	struct device			*dev;
	struct fsl_ifc_global __iomem	*gregs;
	struct fsl_ifc_runtime __iomem	*rregs;
	int				irq;
	int				nand_irq;
	spinlock_t			lock;
	void				*nand;
	int				version;
	int				banks;

u32 nand_stat;
	wait_queue_head_t nand_wait;
	bool little_endian;
};

extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;

static inline u32 ifc_in32(void __iomem *addr)
{
	u32 val;

if (fsl_ifc_ctrl_dev->little_endian)
		val = ioread32(addr);
	else
		val = ioread32be(addr);

return val;
}

static inline u16 ifc_in16(void __iomem *addr)
{
	u16 val;

if (fsl_ifc_ctrl_dev->little_endian)
		val = ioread16(addr);
	else
		val = ioread16be(addr);

return val;
}

static inline u8 ifc_in8(void __iomem *addr)
{
	return ioread8(addr);
}

static inline void ifc_out32(u32 val, void __iomem *addr)
{
	if (fsl_ifc_ctrl_dev->little_endian)
		iowrite32(val, addr);
	else
		iowrite32be(val, addr);
}

static inline void ifc_out16(u16 val, void __iomem *addr)
{
	if (fsl_ifc_ctrl_dev->little_endian)
		iowrite16(val, addr);
	else
		iowrite16be(val, addr);
}

static inline void ifc_out8(u8 val, void __iomem *addr)
{
	iowrite8(val, addr);
}

#endif /* __ASM_FSL_IFC_H */

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