/
usr
/
src
/
linux-headers-5.15.0-181
/
include
/
linux
/
/usr/src/linux-headers-5.15.0-181/include/linux
mkdir
upload
Name
Size
Mode
Actions
amba/
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0755
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atomic/
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avf/
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0755
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bcma/
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byteorder/
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can/
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ceph/
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clk/
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crush/
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decompress/
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device/
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dma/
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dsa/
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extcon/
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firmware/
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fpga/
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fsl/
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gpio/
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greybus/
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hsi/
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i3c/
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iio/
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input/
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irqchip/
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isdn/
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lockd/
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mailbox/
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mdio/
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mfd/
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mlx4/
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mlx5/
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mmc/
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mtd/
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mux/
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net/
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netfilter/
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netfilter_arp/
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netfilter_bridge/
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netfilter_ipv4/
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netfilter_ipv6/
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pcs/
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perf/
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phy/
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pinctrl/
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platform_data/
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power/
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qed/
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raid/
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regulator/
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remoteproc/
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reset/
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rpmsg/
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rtc/
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sched/
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soc/
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soundwire/
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spi/
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ssb/
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sunrpc/
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surface_aggregator/
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ulpi/
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unaligned/
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usb/
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0755
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8250_pci.h
1038
0644
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dl
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a.out.h
354
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dl
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acct.h
2551
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acpi.h
40902
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acpi_dma.h
3154
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acpi_iort.h
2403
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acpi_mdio.h
819
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acpi_pmtmr.h
674
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acpi_viot.h
478
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adb.h
1832
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dl
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adfs_fs.h
574
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dl
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adreno-smmu-priv.h
2807
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adxl.h
310
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dl
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aer.h
1822
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dl
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agpgart.h
3881
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agp_backend.h
3534
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ahci-remap.h
607
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ahci_platform.h
1747
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dl
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aio.h
651
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dl
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alarmtimer.h
1990
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alcor_pci.h
9043
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align.h
552
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altera_jtaguart.h
379
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altera_uart.h
397
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dl
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amd-iommu.h
6325
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dl
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anon_inodes.h
670
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dl
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apm-emulation.h
1599
0644
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dl
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apm_bios.h
2305
0644
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dl
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apple-gmux.h
918
0644
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dl
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apple_bl.h
498
0644
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dl
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arch_topology.h
2551
0644
edit
dl
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arm-cci.h
1390
0644
edit
dl
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arm-smccc.h
17382
0644
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dl
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armada-37xx-rwtm-mailbox.h
431
0644
edit
dl
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arm_ffa.h
7545
0644
edit
dl
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arm_sdei.h
2730
0644
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dl
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array_size.h
332
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dl
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ascii85.h
555
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dl
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asn1.h
1832
0644
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dl
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asn1_ber_bytecode.h
2576
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dl
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asn1_decoder.h
468
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dl
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asn1_encoder.h
1006
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dl
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assoc_array.h
2949
0644
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dl
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assoc_array_priv.h
5423
0644
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dl
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async.h
4439
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dl
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async_tx.h
6860
0644
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dl
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ata.h
33799
0644
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dl
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atalk.h
4586
0644
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dl
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ata_platform.h
749
0644
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dl
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ath9k_platform.h
1477
0644
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dl
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atm.h
287
0644
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dl
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atmdev.h
10477
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dl
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atmel-isc-media.h
2115
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dl
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atmel-mci.h
1429
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dl
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atmel-ssc.h
9971
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dl
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atmel_pdc.h
1295
0644
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dl
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atm_tcp.h
511
0644
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dl
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atomic.h
2644
0644
edit
dl
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attribute_container.h
2803
0644
edit
dl
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audit.h
19921
0644
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dl
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auto_dev-ioctl.h
296
0644
edit
dl
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auto_fs.h
278
0644
edit
dl
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auxiliary_bus.h
2539
0644
edit
dl
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auxvec.h
304
0644
edit
dl
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average.h
2481
0644
edit
dl
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backing-dev-defs.h
8753
0644
edit
dl
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backing-dev.h
12189
0644
edit
dl
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backlight.h
13447
0644
edit
dl
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badblocks.h
2188
0644
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dl
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balloon_compaction.h
5892
0644
edit
dl
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bcd.h
559
0644
edit
dl
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bch.h
2152
0644
edit
dl
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bcm47xx_nvram.h
1033
0644
edit
dl
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bcm47xx_sprom.h
616
0644
edit
dl
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bcm47xx_wdt.h
555
0644
edit
dl
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bcm963xx_nvram.h
3036
0644
edit
dl
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bcm963xx_tag.h
3685
0644
edit
dl
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binfmts.h
4683
0644
edit
dl
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bio.h
20108
0644
edit
dl
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bitfield.h
5460
0644
edit
dl
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bitmap.h
22664
0644
edit
dl
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bitops.h
8733
0644
edit
dl
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bitrev.h
2594
0644
edit
dl
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bits.h
1387
0644
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dl
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bit_spinlock.h
2360
0644
edit
dl
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blk-cgroup.h
22648
0644
edit
dl
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blk-crypto.h
4117
0644
edit
dl
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blk-mq-pci.h
269
0644
edit
dl
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blk-mq-rdma.h
273
0644
edit
dl
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blk-mq-virtio.h
293
0644
edit
dl
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blk-mq.h
19834
0644
edit
dl
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blk-pm.h
708
0644
edit
dl
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blkdev.h
58041
0644
edit
dl
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blkpg.h
436
0644
edit
dl
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blktrace_api.h
3858
0644
edit
dl
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blk_types.h
15669
0644
edit
dl
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blockgroup_lock.h
810
0644
edit
dl
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bma150.h
1286
0644
edit
dl
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bootconfig.h
8712
0644
edit
dl
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bootmem_info.h
1733
0644
edit
dl
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bottom_half.h
974
0644
edit
dl
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bpf-cgroup.h
18796
0644
edit
dl
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bpf-netns.h
1559
0644
edit
dl
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bpf.h
76212
0644
edit
dl
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bpfilter.h
791
0644
edit
dl
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bpfptr.h
2029
0644
edit
dl
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bpf_lirc.h
698
0644
edit
dl
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bpf_local_storage.h
5359
0644
edit
dl
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bpf_lsm.h
1456
0644
edit
dl
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bpf_trace.h
166
0644
edit
dl
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bpf_types.h
5536
0644
edit
dl
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bpf_verifier.h
20865
0644
edit
dl
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brcmphy.h
13994
0644
edit
dl
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bsearch.h
624
0644
edit
dl
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bsg-lib.h
1759
0644
edit
dl
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bsg.h
492
0644
edit
dl
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btf.h
7432
0644
edit
dl
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btf_ids.h
5463
0644
edit
dl
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btree-128.h
2737
0644
edit
dl
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btree-type.h
3991
0644
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dl
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btree.h
7000
0644
edit
dl
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btrfs.h
145
0644
edit
dl
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buffer_head.h
14814
0644
edit
dl
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bug.h
2220
0644
edit
dl
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build-salt.h
375
0644
edit
dl
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buildid.h
561
0644
edit
dl
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build_bug.h
2823
0644
edit
dl
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bvec.h
6319
0644
edit
dl
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c2port.h
1384
0644
edit
dl
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cache.h
2616
0644
edit
dl
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cacheinfo.h
3837
0644
edit
dl
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capability.h
8486
0644
edit
dl
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cb710.h
5490
0644
edit
dl
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cciss_ioctl.h
1053
0644
edit
dl
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ccp.h
18577
0644
edit
dl
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cc_platform.h
2378
0644
edit
dl
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cdev.h
845
0644
edit
dl
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cdrom.h
9197
0644
edit
dl
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cfag12864b.h
1509
0644
edit
dl
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cfi.h
1152
0644
edit
dl
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cgroup-defs.h
24815
0644
edit
dl
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cgroup.h
28840
0644
edit
dl
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cgroup_rdma.h
1206
0644
edit
dl
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cgroup_subsys.h
1259
0644
edit
dl
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circ_buf.h
1120
0644
edit
dl
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cleancache.h
3982
0644
edit
dl
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cleanup.h
4986
0644
edit
dl
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clk-provider.h
59330
0644
edit
dl
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clk.h
34418
0644
edit
dl
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clkdev.h
1322
0644
edit
dl
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clockchips.h
7445
0644
edit
dl
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clocksource.h
10227
0644
edit
dl
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clocksource_ids.h
247
0644
edit
dl
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cm4000_cs.h
199
0644
edit
dl
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cma.h
2004
0644
edit
dl
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cnt32_to_63.h
3545
0644
edit
dl
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cn_proc.h
1890
0644
edit
dl
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coda.h
2215
0644
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dl
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compaction.h
7319
0644
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dl
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compat.h
32122
0644
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dl
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compiler-clang.h
4150
0644
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dl
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compiler-gcc.h
5021
0644
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dl
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compiler-intel.h
949
0644
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dl
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compiler-version.h
517
0644
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dl
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compiler.h
8553
0644
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dl
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compiler_attributes.h
13557
0644
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dl
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compiler_types.h
11023
0644
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dl
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completion.h
4101
0644
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dl
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component.h
4163
0644
edit
dl
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configfs.h
8683
0644
edit
dl
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connector.h
3927
0644
edit
dl
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console.h
7758
0644
edit
dl
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consolemap.h
1076
0644
edit
dl
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console_struct.h
7253
0644
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dl
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const.h
421
0644
edit
dl
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container.h
610
0644
edit
dl
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context_tracking.h
3362
0644
edit
dl
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context_tracking_state.h
1616
0644
edit
dl
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cookie.h
1254
0644
edit
dl
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cordic.h
2132
0644
edit
dl
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coredump.h
1154
0644
edit
dl
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coresight-pmu.h
1355
0644
edit
dl
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coresight-stm.h
152
0644
edit
dl
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coresight.h
18449
0644
edit
dl
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counter.h
15318
0644
edit
dl
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count_zeros.h
1453
0644
edit
dl
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cper.h
16947
0644
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dl
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cpu.h
8485
0644
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dl
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cpufeature.h
1751
0644
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dl
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cpufreq.h
33551
0644
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dl
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cpuhotplug.h
16949
0644
edit
dl
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cpuidle.h
10516
0644
edit
dl
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cpuidle_haltpoll.h
312
0644
edit
dl
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cpumask.h
30089
0644
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dl
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cpuset.h
8351
0644
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dl
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cpu_cooling.h
1901
0644
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dl
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cpu_pm.h
2433
0644
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dl
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cpu_rmap.h
1721
0644
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crash_core.h
3465
0644
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dl
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crash_dump.h
4149
0644
edit
dl
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crc-ccitt.h
609
0644
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dl
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crc-itu-t.h
531
0644
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dl
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crc-t10dif.h
453
0644
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dl
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crc4.h
192
0644
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crc7.h
316
0644
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crc8.h
3747
0644
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dl
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crc16.h
540
0644
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dl
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crc32.h
2894
0644
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dl
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crc32c.h
331
0644
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dl
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crc32poly.h
610
0644
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dl
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crc64.h
280
0644
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dl
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cred.h
12804
0644
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dl
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crypto.h
27890
0644
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dl
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cs5535.h
6277
0644
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dl
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ctype.h
1912
0644
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dl
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cuda.h
613
0644
edit
dl
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damon.h
10601
0644
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dl
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dasd_mod.h
204
0644
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dl
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davinci_emac.h
1080
0644
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dl
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dax.h
6719
0644
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dl
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dca.h
1922
0644
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dl
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dcache.h
19076
0644
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dl
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dccp.h
10988
0644
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dl
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debugfs.h
12253
0644
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dl
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debugobjects.h
4085
0644
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dl
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debug_locks.h
1627
0644
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dl
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delay.h
2490
0644
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dl
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delayacct.h
5584
0644
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dl
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delayed_call.h
709
0644
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dl
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devcoredump.h
2266
0644
edit
dl
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devfreq-event.h
6095
0644
edit
dl
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devfreq.h
14370
0644
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dl
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devfreq_cooling.h
2763
0644
edit
dl
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device-mapper.h
19371
0644
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dl
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device.h
33997
0644
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dl
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device_cgroup.h
1609
0644
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dl
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devm-helpers.h
2740
0644
edit
dl
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devpts_fs.h
1156
0644
edit
dl
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dev_printk.h
9406
0644
edit
dl
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dfl.h
2435
0644
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dl
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digsig.h
1212
0644
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dl
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dim.h
9421
0644
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dl
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dio.h
11019
0644
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dl
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dirent.h
215
0644
edit
dl
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dlm.h
6005
0644
edit
dl
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dlm_plock.h
532
0644
edit
dl
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dm-bufio.h
4992
0644
edit
dl
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dm-dirty-log.h
4038
0644
edit
dl
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dm-io.h
1980
0644
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dl
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dm-kcopyd.h
3013
0644
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dl
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dm-region-hash.h
3182
0644
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dl
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dm9000.h
987
0644
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dl
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dma-buf-map.h
8318
0644
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dl
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dma-buf.h
20962
0644
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dl
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dma-direct.h
3681
0644
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dl
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dma-direction.h
407
0644
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dl
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dma-fence-array.h
2191
0644
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dl
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dma-fence-chain.h
3144
0644
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dl
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dma-fence.h
21357
0644
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dl
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dma-heap.h
1616
0644
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dl
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dma-iommu.h
2265
0644
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dl
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dma-map-ops.h
13197
0644
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dl
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dma-mapping.h
20589
0644
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dl
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dma-resv.h
12236
0644
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dl
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dmaengine.h
54851
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dl
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dmapool.h
1832
0644
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dl
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dmar.h
7929
0644
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dl
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dmi.h
4372
0644
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dl
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dnotify.h
1044
0644
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dl
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dns_resolver.h
1390
0644
edit
dl
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dqblk_qtree.h
2238
0644
edit
dl
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dqblk_v1.h
327
0644
edit
dl
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dqblk_v2.h
406
0644
edit
dl
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drbd.h
10311
0644
edit
dl
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drbd_genl.h
22010
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edit
dl
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drbd_genl_api.h
1808
0644
edit
dl
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drbd_limits.h
8003
0644
edit
dl
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ds2782_battery.h
158
0644
edit
dl
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dtlk.h
3584
0644
edit
dl
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dtpm.h
1684
0644
edit
dl
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dw_apb_timer.h
1566
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edit
dl
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dynamic_debug.h
6471
0644
edit
dl
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dynamic_queue_limits.h
3812
0644
edit
dl
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earlycpio.h
359
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edit
dl
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ecryptfs.h
3915
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dl
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edac.h
19924
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dl
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edd.h
1077
0644
edit
dl
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eeprom_93cx6.h
2707
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edit
dl
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eeprom_93xx46.h
1062
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edit
dl
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efi-bgrt.h
644
0644
edit
dl
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efi.h
43038
0644
edit
dl
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efi_embedded_fw.h
1060
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edit
dl
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efs_vh.h
1585
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edit
dl
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eisa.h
3031
0644
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dl
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elevator.h
5653
0644
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dl
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elf-fdpic.h
2030
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Edit:
/usr/src/linux-headers-5.15.0-181/include/linux/rio_regs.h
(19524B)
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * RapidIO register definitions * * Copyright 2005 MontaVista Software, Inc. * Matt Porter <mporter@kernel.crashing.org> */ #ifndef LINUX_RIO_REGS_H #define LINUX_RIO_REGS_H /* * In RapidIO, each device has a 16MB configuration space that is * accessed via maintenance transactions. Portions of configuration * space are standardized and/or reserved. */ #define RIO_MAINT_SPACE_SZ 0x1000000 /* 16MB of RapidIO mainenance space */ #define RIO_DEV_ID_CAR 0x00 /* [I] Device Identity CAR */ #define RIO_DEV_INFO_CAR 0x04 /* [I] Device Information CAR */ #define RIO_ASM_ID_CAR 0x08 /* [I] Assembly Identity CAR */ #define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */ #define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */ #define RIO_ASM_INFO_CAR 0x0c /* [I] Assembly Information CAR */ #define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */ #define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */ #define RIO_PEF_CAR 0x10 /* [I] Processing Element Features CAR */ #define RIO_PEF_BRIDGE 0x80000000 /* [I] Bridge */ #define RIO_PEF_MEMORY 0x40000000 /* [I] MMIO */ #define RIO_PEF_PROCESSOR 0x20000000 /* [I] Processor */ #define RIO_PEF_SWITCH 0x10000000 /* [I] Switch */ #define RIO_PEF_MULTIPORT 0x08000000 /* [VI, 2.1] Multiport */ #define RIO_PEF_INB_MBOX 0x00f00000 /* [II, <= 1.2] Mailboxes */ #define RIO_PEF_INB_MBOX0 0x00800000 /* [II, <= 1.2] Mailbox 0 */ #define RIO_PEF_INB_MBOX1 0x00400000 /* [II, <= 1.2] Mailbox 1 */ #define RIO_PEF_INB_MBOX2 0x00200000 /* [II, <= 1.2] Mailbox 2 */ #define RIO_PEF_INB_MBOX3 0x00100000 /* [II, <= 1.2] Mailbox 3 */ #define RIO_PEF_INB_DOORBELL 0x00080000 /* [II, <= 1.2] Doorbells */ #define RIO_PEF_DEV32 0x00001000 /* [III] PE supports Common TRansport Dev32 */ #define RIO_PEF_EXT_RT 0x00000200 /* [III, 1.3] Extended route table support */ #define RIO_PEF_STD_RT 0x00000100 /* [III, 1.3] Standard route table support */ #define RIO_PEF_CTLS 0x00000010 /* [III] Common Transport Large System (< rev.3) */ #define RIO_PEF_DEV16 0x00000010 /* [III] PE Supports Common Transport Dev16 (rev.3) */ #define RIO_PEF_EXT_FEATURES 0x00000008 /* [I] EFT_PTR valid */ #define RIO_PEF_ADDR_66 0x00000004 /* [I] 66 bits */ #define RIO_PEF_ADDR_50 0x00000002 /* [I] 50 bits */ #define RIO_PEF_ADDR_34 0x00000001 /* [I] 34 bits */ #define RIO_SWP_INFO_CAR 0x14 /* [I] Switch Port Information CAR */ #define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00 /* [I] Total number of ports */ #define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff /* [I] Maintenance transaction port number */ #define RIO_GET_TOTAL_PORTS(x) ((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8) #define RIO_GET_PORT_NUM(x) (x & RIO_SWP_INFO_PORT_NUM_MASK) #define RIO_SRC_OPS_CAR 0x18 /* [I] Source Operations CAR */ #define RIO_SRC_OPS_READ 0x00008000 /* [I] Read op */ #define RIO_SRC_OPS_WRITE 0x00004000 /* [I] Write op */ #define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */ #define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */ #define RIO_SRC_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */ #define RIO_SRC_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */ #define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */ #define RIO_SRC_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */ #define RIO_SRC_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */ #define RIO_SRC_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */ #define RIO_SRC_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */ #define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */ #define RIO_DST_OPS_CAR 0x1c /* Destination Operations CAR */ #define RIO_DST_OPS_READ 0x00008000 /* [I] Read op */ #define RIO_DST_OPS_WRITE 0x00004000 /* [I] Write op */ #define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */ #define RIO_DST_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */ #define RIO_DST_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */ #define RIO_DST_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */ #define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */ #define RIO_DST_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */ #define RIO_DST_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */ #define RIO_DST_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */ #define RIO_DST_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */ #define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */ #define RIO_OPS_READ 0x00008000 /* [I] Read op */ #define RIO_OPS_WRITE 0x00004000 /* [I] Write op */ #define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */ #define RIO_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */ #define RIO_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */ #define RIO_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */ #define RIO_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */ #define RIO_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */ #define RIO_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */ #define RIO_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */ #define RIO_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */ #define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */ /* 0x20-0x30 *//* Reserved */ #define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */ #define RIO_RT_MAX_DESTID 0x0000ffff #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */ #define RIO_MBOX0_AVAIL 0x80000000 /* [II] Mbox 0 avail */ #define RIO_MBOX0_FULL 0x40000000 /* [II] Mbox 0 full */ #define RIO_MBOX0_EMPTY 0x20000000 /* [II] Mbox 0 empty */ #define RIO_MBOX0_BUSY 0x10000000 /* [II] Mbox 0 busy */ #define RIO_MBOX0_FAIL 0x08000000 /* [II] Mbox 0 fail */ #define RIO_MBOX0_ERROR 0x04000000 /* [II] Mbox 0 error */ #define RIO_MBOX1_AVAIL 0x00800000 /* [II] Mbox 1 avail */ #define RIO_MBOX1_FULL 0x00200000 /* [II] Mbox 1 full */ #define RIO_MBOX1_EMPTY 0x00200000 /* [II] Mbox 1 empty */ #define RIO_MBOX1_BUSY 0x00100000 /* [II] Mbox 1 busy */ #define RIO_MBOX1_FAIL 0x00080000 /* [II] Mbox 1 fail */ #define RIO_MBOX1_ERROR 0x00040000 /* [II] Mbox 1 error */ #define RIO_MBOX2_AVAIL 0x00008000 /* [II] Mbox 2 avail */ #define RIO_MBOX2_FULL 0x00004000 /* [II] Mbox 2 full */ #define RIO_MBOX2_EMPTY 0x00002000 /* [II] Mbox 2 empty */ #define RIO_MBOX2_BUSY 0x00001000 /* [II] Mbox 2 busy */ #define RIO_MBOX2_FAIL 0x00000800 /* [II] Mbox 2 fail */ #define RIO_MBOX2_ERROR 0x00000400 /* [II] Mbox 2 error */ #define RIO_MBOX3_AVAIL 0x00000080 /* [II] Mbox 3 avail */ #define RIO_MBOX3_FULL 0x00000040 /* [II] Mbox 3 full */ #define RIO_MBOX3_EMPTY 0x00000020 /* [II] Mbox 3 empty */ #define RIO_MBOX3_BUSY 0x00000010 /* [II] Mbox 3 busy */ #define RIO_MBOX3_FAIL 0x00000008 /* [II] Mbox 3 fail */ #define RIO_MBOX3_ERROR 0x00000004 /* [II] Mbox 3 error */ #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */ #define RIO_DOORBELL_CSR 0x44 /* [II, <= 1.2] Doorbell CSR */ #define RIO_DOORBELL_AVAIL 0x80000000 /* [II] Doorbell avail */ #define RIO_DOORBELL_FULL 0x40000000 /* [II] Doorbell full */ #define RIO_DOORBELL_EMPTY 0x20000000 /* [II] Doorbell empty */ #define RIO_DOORBELL_BUSY 0x10000000 /* [II] Doorbell busy */ #define RIO_DOORBELL_FAILED 0x08000000 /* [II] Doorbell failed */ #define RIO_DOORBELL_ERROR 0x04000000 /* [II] Doorbell error */ #define RIO_WRITE_PORT_AVAILABLE 0x00000080 /* [I] Write Port Available */ #define RIO_WRITE_PORT_FULL 0x00000040 /* [I] Write Port Full */ #define RIO_WRITE_PORT_EMPTY 0x00000020 /* [I] Write Port Empty */ #define RIO_WRITE_PORT_BUSY 0x00000010 /* [I] Write Port Busy */ #define RIO_WRITE_PORT_FAILED 0x00000008 /* [I] Write Port Failed */ #define RIO_WRITE_PORT_ERROR 0x00000004 /* [I] Write Port Error */ /* 0x48 *//* Reserved */ #define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */ #define RIO_PELL_ADDR_66 0x00000004 /* [I] 66-bit addr */ #define RIO_PELL_ADDR_50 0x00000002 /* [I] 50-bit addr */ #define RIO_PELL_ADDR_34 0x00000001 /* [I] 34-bit addr */ /* 0x50-0x54 *//* Reserved */ #define RIO_LCSH_BA 0x58 /* [I] LCS High Base Address */ #define RIO_LCSL_BA 0x5c /* [I] LCS Base Address */ #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */ /* 0x64 *//* Reserved */ #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */ #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */ #define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70 #define RIO_STD_RTE_CONF_EXTCFGEN 0x80000000 #define RIO_STD_RTE_CONF_PORT_SEL_CSR 0x74 #define RIO_STD_RTE_DEFAULT_PORT 0x78 /* 0x7c-0xf8 *//* Reserved */ /* 0x100-0xfff8 *//* [I] Extended Features Space */ /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */ /* * Extended Features Space is a configuration space area where * functionality is mapped into extended feature blocks via a * singly linked list of extended feature pointers (EFT_PTR). * * Each extended feature block can be identified/located in * Extended Features Space by walking the extended feature * list starting with the Extended Feature Pointer located * in the Assembly Information CAR. * * Extended Feature Blocks (EFBs) are identified with an assigned * EFB ID. Extended feature block offsets in the definitions are * relative to the offset of the EFB within the Extended Features * Space. */ /* Helper macros to parse the Extended Feature Block header */ #define RIO_EFB_PTR_MASK 0xffff0000 #define RIO_EFB_ID_MASK 0x0000ffff #define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16) #define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK) /* Extended Feature Block IDs */ #define RIO_EFB_SER_EP_M1_ID 0x0001 /* [VI] LP-Serial EP Devices, Map I */ #define RIO_EFB_SER_EP_SW_M1_ID 0x0002 /* [VI] LP-Serial EP w SW Recovery Devices, Map I */ #define RIO_EFB_SER_EPF_M1_ID 0x0003 /* [VI] LP-Serial EP Free Devices, Map I */ #define RIO_EFB_SER_EP_ID 0x0004 /* [VI] LP-Serial EP Devices, RIO 1.2 */ #define RIO_EFB_SER_EP_REC_ID 0x0005 /* [VI] LP-Serial EP w SW Recovery Devices, RIO 1.2 */ #define RIO_EFB_SER_EP_FREE_ID 0x0006 /* [VI] LP-Serial EP Free Devices, RIO 1.2 */ #define RIO_EFB_ERR_MGMNT 0x0007 /* [VIII] Error Management Extensions */ #define RIO_EFB_SER_EPF_SW_M1_ID 0x0009 /* [VI] LP-Serial EP Free w SW Recovery Devices, Map I */ #define RIO_EFB_SW_ROUTING_TBL 0x000E /* [III] Switch Routing Table Block */ #define RIO_EFB_SER_EP_M2_ID 0x0011 /* [VI] LP-Serial EP Devices, Map II */ #define RIO_EFB_SER_EP_SW_M2_ID 0x0012 /* [VI] LP-Serial EP w SW Recovery Devices, Map II */ #define RIO_EFB_SER_EPF_M2_ID 0x0013 /* [VI] LP-Serial EP Free Devices, Map II */ #define RIO_EFB_ERR_MGMNT_HS 0x0017 /* [VIII] Error Management Extensions, Hot-Swap only */ #define RIO_EFB_SER_EPF_SW_M2_ID 0x0019 /* [VI] LP-Serial EP Free w SW Recovery Devices, Map II */ /* * Physical LP-Serial Registers Definitions * Parameters in register macros: * n - port number, m - Register Map Type (1 or 2) */ #define RIO_PORT_MNT_HEADER 0x0000 #define RIO_PORT_REQ_CTL_CSR 0x0020 #define RIO_PORT_RSP_CTL_CSR 0x0024 #define RIO_PORT_LINKTO_CTL_CSR 0x0020 #define RIO_PORT_RSPTO_CTL_CSR 0x0024 #define RIO_PORT_GEN_CTL_CSR 0x003c #define RIO_PORT_GEN_HOST 0x80000000 #define RIO_PORT_GEN_MASTER 0x40000000 #define RIO_PORT_GEN_DISCOVERED 0x20000000 #define RIO_PORT_N_MNT_REQ_CSR(n, m) (0x40 + (n) * (0x20 * (m))) #define RIO_MNT_REQ_CMD_RD 0x03 /* Reset-device command */ #define RIO_MNT_REQ_CMD_IS 0x04 /* Input-status command */ #define RIO_PORT_N_MNT_RSP_CSR(n, m) (0x44 + (n) * (0x20 * (m))) #define RIO_PORT_N_MNT_RSP_RVAL 0x80000000 /* Response Valid */ #define RIO_PORT_N_MNT_RSP_ASTAT 0x000007e0 /* ackID Status */ #define RIO_PORT_N_MNT_RSP_LSTAT 0x0000001f /* Link Status */ #define RIO_PORT_N_ACK_STS_CSR(n) (0x48 + (n) * 0x20) /* Only in RM-I */ #define RIO_PORT_N_ACK_CLEAR 0x80000000 #define RIO_PORT_N_ACK_INBOUND 0x3f000000 #define RIO_PORT_N_ACK_OUTSTAND 0x00003f00 #define RIO_PORT_N_ACK_OUTBOUND 0x0000003f #define RIO_PORT_N_CTL2_CSR(n, m) (0x54 + (n) * (0x20 * (m))) #define RIO_PORT_N_CTL2_SEL_BAUD 0xf0000000 #define RIO_PORT_N_ERR_STS_CSR(n, m) (0x58 + (n) * (0x20 * (m))) #define RIO_PORT_N_ERR_STS_OUT_ES 0x00010000 /* Output Error-stopped */ #define RIO_PORT_N_ERR_STS_INP_ES 0x00000100 /* Input Error-stopped */ #define RIO_PORT_N_ERR_STS_PW_PEND 0x00000010 /* Port-Write Pending */ #define RIO_PORT_N_ERR_STS_PORT_UA 0x00000008 /* Port Unavailable */ #define RIO_PORT_N_ERR_STS_PORT_ERR 0x00000004 #define RIO_PORT_N_ERR_STS_PORT_OK 0x00000002 #define RIO_PORT_N_ERR_STS_PORT_UNINIT 0x00000001 #define RIO_PORT_N_CTL_CSR(n, m) (0x5c + (n) * (0x20 * (m))) #define RIO_PORT_N_CTL_PWIDTH 0xc0000000 #define RIO_PORT_N_CTL_PWIDTH_1 0x00000000 #define RIO_PORT_N_CTL_PWIDTH_4 0x40000000 #define RIO_PORT_N_CTL_IPW 0x38000000 /* Initialized Port Width */ #define RIO_PORT_N_CTL_P_TYP_SER 0x00000001 #define RIO_PORT_N_CTL_LOCKOUT 0x00000002 #define RIO_PORT_N_CTL_EN_RX 0x00200000 #define RIO_PORT_N_CTL_EN_TX 0x00400000 #define RIO_PORT_N_OB_ACK_CSR(n) (0x60 + (n) * 0x40) /* Only in RM-II */ #define RIO_PORT_N_OB_ACK_CLEAR 0x80000000 #define RIO_PORT_N_OB_ACK_OUTSTD 0x00fff000 #define RIO_PORT_N_OB_ACK_OUTBND 0x00000fff #define RIO_PORT_N_IB_ACK_CSR(n) (0x64 + (n) * 0x40) /* Only in RM-II */ #define RIO_PORT_N_IB_ACK_INBND 0x00000fff /* * Device-based helper macros for serial port register access. * d - pointer to rapidio device object, n - port number */ #define RIO_DEV_PORT_N_MNT_REQ_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_MNT_REQ_CSR(n, d->phys_rmap)) #define RIO_DEV_PORT_N_MNT_RSP_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(n, d->phys_rmap)) #define RIO_DEV_PORT_N_ACK_STS_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_ACK_STS_CSR(n)) #define RIO_DEV_PORT_N_CTL2_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_CTL2_CSR(n, d->phys_rmap)) #define RIO_DEV_PORT_N_ERR_STS_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_ERR_STS_CSR(n, d->phys_rmap)) #define RIO_DEV_PORT_N_CTL_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_CTL_CSR(n, d->phys_rmap)) #define RIO_DEV_PORT_N_OB_ACK_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_OB_ACK_CSR(n)) #define RIO_DEV_PORT_N_IB_ACK_CSR(d, n) \ (d->phys_efptr + RIO_PORT_N_IB_ACK_CSR(n)) /* * Error Management Extensions (RapidIO 1.3+, Part 8) * * Extended Features Block ID=0x0007 */ /* General EM Registers (Common for all Ports) */ #define RIO_EM_EFB_HEADER 0x000 /* Error Management Extensions Block Header */ #define RIO_EM_EMHS_CAR 0x004 /* EM Functionality CAR */ #define RIO_EM_LTL_ERR_DETECT 0x008 /* Logical/Transport Layer Error Detect CSR */ #define RIO_EM_LTL_ERR_EN 0x00c /* Logical/Transport Layer Error Enable CSR */ #define REM_LTL_ERR_ILLTRAN 0x08000000 /* Illegal Transaction decode */ #define REM_LTL_ERR_UNSOLR 0x00800000 /* Unsolicited Response */ #define REM_LTL_ERR_UNSUPTR 0x00400000 /* Unsupported Transaction */ #define REM_LTL_ERR_IMPSPEC 0x000000ff /* Implementation Specific */ #define RIO_EM_LTL_HIADDR_CAP 0x010 /* Logical/Transport Layer High Address Capture CSR */ #define RIO_EM_LTL_ADDR_CAP 0x014 /* Logical/Transport Layer Address Capture CSR */ #define RIO_EM_LTL_DEVID_CAP 0x018 /* Logical/Transport Layer Device ID Capture CSR */ #define RIO_EM_LTL_CTRL_CAP 0x01c /* Logical/Transport Layer Control Capture CSR */ #define RIO_EM_LTL_DID32_CAP 0x020 /* Logical/Transport Layer Dev32 DestID Capture CSR */ #define RIO_EM_LTL_SID32_CAP 0x024 /* Logical/Transport Layer Dev32 source ID Capture CSR */ #define RIO_EM_PW_TGT_DEVID 0x028 /* Port-write Target deviceID CSR */ #define RIO_EM_PW_TGT_DEVID_D16M 0xff000000 /* Port-write Target DID16 MSB */ #define RIO_EM_PW_TGT_DEVID_D8 0x00ff0000 /* Port-write Target DID16 LSB or DID8 */ #define RIO_EM_PW_TGT_DEVID_DEV16 0x00008000 /* Port-write Target DID16 LSB or DID8 */ #define RIO_EM_PW_TGT_DEVID_DEV32 0x00004000 /* Port-write Target DID16 LSB or DID8 */ #define RIO_EM_PKT_TTL 0x02c /* Packet Time-to-live CSR */ #define RIO_EM_PKT_TTL_VAL 0xffff0000 /* Packet Time-to-live value */ #define RIO_EM_PW_TGT32_DEVID 0x030 /* Port-write Dev32 Target deviceID CSR */ #define RIO_EM_PW_TX_CTRL 0x034 /* Port-write Transmission Control CSR */ #define RIO_EM_PW_TX_CTRL_PW_DIS 0x00000001 /* Port-write Transmission Disable bit */ /* Per-Port EM Registers */ #define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40) /* Port N Error Detect CSR */ #define REM_PED_IMPL_SPEC 0x80000000 #define REM_PED_LINK_OK2U 0x40000000 /* Link OK to Uninit transition */ #define REM_PED_LINK_UPDA 0x20000000 /* Link Uninit Packet Discard Active */ #define REM_PED_LINK_U2OK 0x10000000 /* Link Uninit to OK transition */ #define REM_PED_LINK_TO 0x00000001 #define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) /* Port N Error Rate Enable CSR */ #define RIO_EM_PN_ERRRATE_EN_OK2U 0x40000000 /* Enable notification for OK2U */ #define RIO_EM_PN_ERRRATE_EN_UPDA 0x20000000 /* Enable notification for UPDA */ #define RIO_EM_PN_ERRRATE_EN_U2OK 0x10000000 /* Enable notification for U2OK */ #define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40) /* Port N Attributes Capture CSR */ #define RIO_EM_PN_PKT_CAP_0(x) (0x04c + x*0x40) /* Port N Packet/Control Symbol Capture 0 CSR */ #define RIO_EM_PN_PKT_CAP_1(x) (0x050 + x*0x40) /* Port N Packet Capture 1 CSR */ #define RIO_EM_PN_PKT_CAP_2(x) (0x054 + x*0x40) /* Port N Packet Capture 2 CSR */ #define RIO_EM_PN_PKT_CAP_3(x) (0x058 + x*0x40) /* Port N Packet Capture 3 CSR */ #define RIO_EM_PN_ERRRATE(x) (0x068 + x*0x40) /* Port N Error Rate CSR */ #define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) /* Port N Error Rate Threshold CSR */ #define RIO_EM_PN_LINK_UDT(x) (0x070 + x*0x40) /* Port N Link Uninit Discard Timer CSR */ #define RIO_EM_PN_LINK_UDT_TO 0xffffff00 /* Link Uninit Timeout value */ /* * Switch Routing Table Register Block ID=0x000E (RapidIO 3.0+, part 3) * Register offsets are defined from beginning of the block. */ /* Broadcast Routing Table Control CSR */ #define RIO_BC_RT_CTL_CSR 0x020 #define RIO_RT_CTL_THREE_LVL 0x80000000 #define RIO_RT_CTL_DEV32_RT_CTRL 0x40000000 #define RIO_RT_CTL_MC_MASK_SZ 0x03000000 /* 3.0+ Part 11: Multicast */ /* Broadcast Level 0 Info CSR */ #define RIO_BC_RT_LVL0_INFO_CSR 0x030 #define RIO_RT_L0I_NUM_GR 0xff000000 #define RIO_RT_L0I_GR_PTR 0x00fffc00 /* Broadcast Level 1 Info CSR */ #define RIO_BC_RT_LVL1_INFO_CSR 0x034 #define RIO_RT_L1I_NUM_GR 0xff000000 #define RIO_RT_L1I_GR_PTR 0x00fffc00 /* Broadcast Level 2 Info CSR */ #define RIO_BC_RT_LVL2_INFO_CSR 0x038 #define RIO_RT_L2I_NUM_GR 0xff000000 #define RIO_RT_L2I_GR_PTR 0x00fffc00 /* Per-Port Routing Table registers. * Register fields defined in the broadcast section above are * applicable to the corresponding registers below. */ #define RIO_SPx_RT_CTL_CSR(x) (0x040 + (0x20 * x)) #define RIO_SPx_RT_LVL0_INFO_CSR(x) (0x50 + (0x20 * x)) #define RIO_SPx_RT_LVL1_INFO_CSR(x) (0x54 + (0x20 * x)) #define RIO_SPx_RT_LVL2_INFO_CSR(x) (0x58 + (0x20 * x)) /* Register Formats for Routing Table Group entry. * Register offsets are calculated using GR_PTR field in the corresponding * table Level_N and group/entry numbers (see RapidIO 3.0+ Part 3). */ #define RIO_RT_Ln_ENTRY_IMPL_DEF 0xf0000000 #define RIO_RT_Ln_ENTRY_RTE_VAL 0x000003ff #define RIO_RT_ENTRY_DROP_PKT 0x300 #endif /* LINUX_RIO_REGS_H */
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