FM / sound

/usr/src/linux-headers-5.15.0-181/include/sound/

/usr/src/linux-headers-5.15.0-181/include/sound

Name	Size	Mode	Actions
ac97/	-	0755	rm
sof/	-	0755	rm
ac97_codec.h	16044	0644	edit dl rm
aci.h	2458	0644	edit dl rm
ad1816a.h	4843	0644	edit dl rm
ad1843.h	1516	0644	edit dl rm
adau1373.h	706	0644	edit dl rm
ak4xxx-adda.h	2724	0644	edit dl rm
ak4113.h	10461	0644	edit dl rm
ak4114.h	9773	0644	edit dl rm
ak4117.h	8542	0644	edit dl rm
ak4531_codec.h	2478	0644	edit dl rm
ak4641.h	476	0644	edit dl rm
alc5623.h	536	0644	edit dl rm
asequencer.h	2975	0644	edit dl rm
asound.h	590	0644	edit dl rm
asoundef.h	16403	0644	edit dl rm
compress_driver.h	7986	0644	edit dl rm
control.h	9958	0644	edit dl rm
core.h	15895	0644	edit dl rm
cs35l33.h	888	0644	edit dl rm
cs35l34.h	741	0644	edit dl rm
cs35l35.h	2267	0644	edit dl rm
cs35l36.h	772	0644	edit dl rm
cs35l41.h	30889	0644	edit dl rm
cs42l42.h	35149	0644	edit dl rm
cs42l52.h	592	0644	edit dl rm
cs42l56.h	1046	0644	edit dl rm
cs42l73.h	361	0644	edit dl rm
cs4231-regs.h	7785	0644	edit dl rm
cs4271.h	961	0644	edit dl rm
cs8403.h	8138	0644	edit dl rm
cs8427.h	9954	0644	edit dl rm
da7213.h	1032	0644	edit dl rm
da7218.h	2468	0644	edit dl rm
da7219-aad.h	2263	0644	edit dl rm
da7219.h	998	0644	edit dl rm
da9055.h	707	0644	edit dl rm
designware_i2s.h	1631	0644	edit dl rm
dmaengine_pcm.h	6913	0644	edit dl rm
emu10k1.h	90722	0644	edit dl rm
emu10k1_synth.h	693	0644	edit dl rm
emu8000.h	3333	0644	edit dl rm
emu8000_reg.h	9767	0644	edit dl rm
emux_legacy.h	4811	0644	edit dl rm
emux_synth.h	6948	0644	edit dl rm
es1688.h	2923	0644	edit dl rm
graph_card.h	271	0644	edit dl rm
gus.h	20119	0644	edit dl rm
hdaudio.h	21538	0644	edit dl rm
hdaudio_ext.h	5680	0644	edit dl rm
hda_chmap.h	2660	0644	edit dl rm
hda_codec.h	17669	0644	edit dl rm
hda_component.h	2085	0644	edit dl rm
hda_hwdep.h	736	0644	edit dl rm
hda_i915.h	589	0644	edit dl rm
hda_register.h	10655	0644	edit dl rm
hda_regmap.h	6934	0644	edit dl rm
hda_verbs.h	17296	0644	edit dl rm
hdmi-codec.h	3011	0644	edit dl rm
hwdep.h	1925	0644	edit dl rm
i2c.h	2857	0644	edit dl rm
info.h	8053	0644	edit dl rm
initval.h	2484	0644	edit dl rm
intel-dsp-config.h	869	0644	edit dl rm
intel-nhlt.h	2851	0644	edit dl rm
jack.h	3172	0644	edit dl rm
l3.h	524	0644	edit dl rm
madera-pdata.h	1996	0644	edit dl rm
max9768.h	729	0644	edit dl rm
max98088.h	1074	0644	edit dl rm
max98090.h	534	0644	edit dl rm
max98095.h	1357	0644	edit dl rm
memalloc.h	2642	0644	edit dl rm
minors.h	3738	0644	edit dl rm
mixer_oss.h	1773	0644	edit dl rm
mpu401.h	3905	0644	edit dl rm
omap-hdmi-audio.h	971	0644	edit dl rm
opl3.h	11909	0644	edit dl rm
opl4.h	459	0644	edit dl rm
pcm-indirect.h	5159	0644	edit dl rm
pcm.h	53684	0644	edit dl rm
pcm_drm_eld.h	183	0644	edit dl rm
pcm_iec958.h	597	0644	edit dl rm
pcm_oss.h	2063	0644	edit dl rm
pcm_params.h	8864	0644	edit dl rm
pt2258.h	513	0644	edit dl rm
pxa2xx-lib.h	2190	0644	edit dl rm
rawmidi.h	5881	0644	edit dl rm
rt286.h	314	0644	edit dl rm
rt298.h	373	0644	edit dl rm
rt1015.h	283	0644	edit dl rm
rt5514.h	399	0644	edit dl rm
rt5659.h	880	0644	edit dl rm
rt5660.h	578	0644	edit dl rm
rt5663.h	476	0644	edit dl rm
rt5665.h	761	0644	edit dl rm
rt5668.h	646	0644	edit dl rm
rt5682.h	901	0644	edit dl rm
s3c24xx_uda134x.h	229	0644	edit dl rm
sb.h	10550	0644	edit dl rm
sb16_csp.h	2100	0644	edit dl rm
seq_device.h	2165	0644	edit dl rm
seq_kernel.h	3378	0644	edit dl rm
seq_midi_emul.h	6757	0644	edit dl rm
seq_midi_event.h	1356	0644	edit dl rm
seq_oss.h	2264	0644	edit dl rm
seq_oss_legacy.h	360	0644	edit dl rm
seq_virmidi.h	2123	0644	edit dl rm
sh_dac_audio.h	441	0644	edit dl rm
sh_fsi.h	693	0644	edit dl rm
simple_card.h	529	0644	edit dl rm
simple_card_utils.h	8351	0644	edit dl rm
snd_wavefront.h	5620	0644	edit dl rm
soc-acpi-intel-match.h	2074	0644	edit dl rm
soc-acpi.h	5637	0644	edit dl rm
soc-card.h	2944	0644	edit dl rm
soc-component.h	19387	0644	edit dl rm
soc-dai.h	19957	0644	edit dl rm
soc-dapm.h	32957	0644	edit dl rm
soc-dpcm.h	5523	0644	edit dl rm
soc-jack.h	3822	0644	edit dl rm
soc-link.h	1172	0644	edit dl rm
soc-topology.h	5835	0644	edit dl rm
soc.h	47899	0644	edit dl rm
sof.h	2596	0644	edit dl rm
soundfont.h	3903	0644	edit dl rm
spear_dma.h	350	0644	edit dl rm
spear_spdif.h	345	0644	edit dl rm
sta32x.h	1015	0644	edit dl rm
sta350.h	1474	0644	edit dl rm
tas2552-plat.h	283	0644	edit dl rm
tas5086.h	210	0644	edit dl rm
tea6330t.h	468	0644	edit dl rm
timer.h	5109	0644	edit dl rm
tlv.h	1627	0644	edit dl rm
tlv320aic3x.h	1777	0644	edit dl rm
tlv320aic32x4.h	1320	0644	edit dl rm
tlv320dac33-plat.h	574	0644	edit dl rm
tpa6130a2-plat.h	291	0644	edit dl rm
uda134x.h	451	0644	edit dl rm
uda1380.h	335	0644	edit dl rm
util_mem.h	1623	0644	edit dl rm
vx_core.h	15055	0644	edit dl rm
wavefront.h	18518	0644	edit dl rm
wm0010.h	466	0644	edit dl rm
wm1250-ev1.h	510	0644	edit dl rm
wm2000.h	479	0644	edit dl rm
wm2200.h	1353	0644	edit dl rm
wm5100.h	1129	0644	edit dl rm
wm8903.h	15377	0644	edit dl rm
wm8904.h	7389	0644	edit dl rm
wm8955.h	442	0644	edit dl rm
wm8960.h	888	0644	edit dl rm
wm8962.h	1694	0644	edit dl rm
wm8993.h	1076	0644	edit dl rm
wm8996.h	1289	0644	edit dl rm
wm9081.h	515	0644	edit dl rm
wm9090.h	634	0644	edit dl rm
wss.h	7949	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/include/sound/ak4113.h (10461B)

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOUND_AK4113_H
#define __SOUND_AK4113_H

/*
 *  Routines for Asahi Kasei AK4113
 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
 *  Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>,
 */

/* AK4113 registers */
/* power down */
#define AK4113_REG_PWRDN	0x00
/* format control */
#define AK4113_REG_FORMAT	0x01
/* input/output control */
#define AK4113_REG_IO0		0x02
/* input/output control */
#define AK4113_REG_IO1		0x03
/* interrupt0 mask */
#define AK4113_REG_INT0_MASK	0x04
/* interrupt1 mask */
#define AK4113_REG_INT1_MASK	0x05
/* DAT mask & DTS select */
#define AK4113_REG_DATDTS	0x06
/* receiver status 0 */
#define AK4113_REG_RCS0		0x07
/* receiver status 1 */
#define AK4113_REG_RCS1		0x08
/* receiver status 2 */
#define AK4113_REG_RCS2		0x09
/* RX channel status byte 0 */
#define AK4113_REG_RXCSB0	0x0a
/* RX channel status byte 1 */
#define AK4113_REG_RXCSB1	0x0b
/* RX channel status byte 2 */
#define AK4113_REG_RXCSB2	0x0c
/* RX channel status byte 3 */
#define AK4113_REG_RXCSB3	0x0d
/* RX channel status byte 4 */
#define AK4113_REG_RXCSB4	0x0e
/* burst preamble Pc byte 0 */
#define AK4113_REG_Pc0		0x0f
/* burst preamble Pc byte 1 */
#define AK4113_REG_Pc1		0x10
/* burst preamble Pd byte 0 */
#define AK4113_REG_Pd0		0x11
/* burst preamble Pd byte 1 */
#define AK4113_REG_Pd1		0x12
/* Q-subcode address + control */
#define AK4113_REG_QSUB_ADDR	0x13
/* Q-subcode track */
#define AK4113_REG_QSUB_TRACK	0x14
/* Q-subcode index */
#define AK4113_REG_QSUB_INDEX	0x15
/* Q-subcode minute */
#define AK4113_REG_QSUB_MINUTE	0x16
/* Q-subcode second */
#define AK4113_REG_QSUB_SECOND	0x17
/* Q-subcode frame */
#define AK4113_REG_QSUB_FRAME	0x18
/* Q-subcode zero */
#define AK4113_REG_QSUB_ZERO	0x19
/* Q-subcode absolute minute */
#define AK4113_REG_QSUB_ABSMIN	0x1a
/* Q-subcode absolute second */
#define AK4113_REG_QSUB_ABSSEC	0x1b
/* Q-subcode absolute frame */
#define AK4113_REG_QSUB_ABSFRM	0x1c

/* sizes */
#define AK4113_REG_RXCSB_SIZE	((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1)
#define AK4113_REG_QSUB_SIZE	((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\
		+1)

#define AK4113_WRITABLE_REGS	(AK4113_REG_DATDTS + 1)

/* AK4113_REG_PWRDN bits */
/* Channel Status Select */
#define AK4113_CS12		(1<<7)
/* Block Start & C/U Output Mode */
#define AK4113_BCU		(1<<6)
/* Master Clock Operation Select */
#define AK4113_CM1		(1<<5)
/* Master Clock Operation Select */
#define AK4113_CM0		(1<<4)
/* Master Clock Frequency Select */
#define AK4113_OCKS1		(1<<3)
/* Master Clock Frequency Select */
#define AK4113_OCKS0		(1<<2)
/* 0 = power down, 1 = normal operation */
#define AK4113_PWN		(1<<1)
/* 0 = reset & initialize (except thisregister), 1 = normal operation */
#define AK4113_RST		(1<<0)

/* AK4113_REQ_FORMAT bits */
/* V/TX Output select: 0 = Validity Flag Output, 1 = TX */
#define AK4113_VTX		(1<<7)
/* Audio Data Control */
#define AK4113_DIF2		(1<<6)
/* Audio Data Control */
#define AK4113_DIF1		(1<<5)
/* Audio Data Control */
#define AK4113_DIF0		(1<<4)
/* Deemphasis Autodetect Enable (1 = enable) */
#define AK4113_DEAU		(1<<3)
/* 32kHz-48kHz Deemphasis Control */
#define AK4113_DEM1		(1<<2)
/* 32kHz-48kHz Deemphasis Control */
#define AK4113_DEM0		(1<<1)
#define AK4113_DEM_OFF		(AK4113_DEM0)
#define AK4113_DEM_44KHZ	(0)
#define AK4113_DEM_48KHZ	(AK4113_DEM1)
#define AK4113_DEM_32KHZ	(AK4113_DEM0|AK4113_DEM1)
/* STDO: 16-bit, right justified */
#define AK4113_DIF_16R		(0)
/* STDO: 18-bit, right justified */
#define AK4113_DIF_18R		(AK4113_DIF0)
/* STDO: 20-bit, right justified */
#define AK4113_DIF_20R		(AK4113_DIF1)
/* STDO: 24-bit, right justified */
#define AK4113_DIF_24R		(AK4113_DIF1|AK4113_DIF0)
/* STDO: 24-bit, left justified */
#define AK4113_DIF_24L		(AK4113_DIF2)
/* STDO: I2S */
#define AK4113_DIF_24I2S	(AK4113_DIF2|AK4113_DIF0)
/* STDO: 24-bit, left justified; LRCLK, BICK = Input */
#define AK4113_DIF_I24L		(AK4113_DIF2|AK4113_DIF1)
/* STDO: I2S;  LRCLK, BICK = Input */
#define AK4113_DIF_I24I2S	(AK4113_DIF2|AK4113_DIF1|AK4113_DIF0)

/* AK4113_REG_IO0 */
/* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
#define AK4113_XTL1		(1<<6)
/* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
#define AK4113_XTL0		(1<<5)
/* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */
#define AK4113_UCE		(1<<4)
/* TX Output Enable (1 = enable) */
#define AK4113_TXE		(1<<3)
/* Output Through Data Selector for TX pin */
#define AK4113_OPS2		(1<<2)
/* Output Through Data Selector for TX pin */
#define AK4113_OPS1		(1<<1)
/* Output Through Data Selector for TX pin */
#define AK4113_OPS0		(1<<0)
/* 11.2896 MHz ref. Xtal freq. */
#define AK4113_XTL_11_2896M	(0)
/* 12.288 MHz ref. Xtal freq. */
#define AK4113_XTL_12_288M	(AK4113_XTL0)
/* 24.576 MHz ref. Xtal freq. */
#define AK4113_XTL_24_576M	(AK4113_XTL1)

/* AK4113_REG_IO1 */
/* Interrupt 0 pin Hold */
#define AK4113_EFH1		(1<<7)
/* Interrupt 0 pin Hold */
#define AK4113_EFH0		(1<<6)
#define AK4113_EFH_512LRCLK	(0)
#define AK4113_EFH_1024LRCLK	(AK4113_EFH0)
#define AK4113_EFH_2048LRCLK	(AK4113_EFH1)
#define AK4113_EFH_4096LRCLK	(AK4113_EFH1|AK4113_EFH0)
/* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */
#define AK4113_FAST		(1<<5)
/* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */
#define AK4113_XMCK		(1<<4)
/* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5  (req. XMCK = 1) */
#define AK4113_DIV		(1<<3)
/* Input Recovery Data Select */
#define AK4113_IPS2		(1<<2)
/* Input Recovery Data Select */
#define AK4113_IPS1		(1<<1)
/* Input Recovery Data Select */
#define AK4113_IPS0		(1<<0)
#define AK4113_IPS(x)		((x)&7)

/* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/
/* mask enable for QINT bit */
#define AK4113_MQI		(1<<7)
/* mask enable for AUTO bit */
#define AK4113_MAUT		(1<<6)
/* mask enable for CINT bit */
#define AK4113_MCIT		(1<<5)
/* mask enable for UNLOCK bit */
#define AK4113_MULK		(1<<4)
/* mask enable for V bit */
#define AK4113_V		(1<<3)
/* mask enable for STC bit */
#define AK4113_STC		(1<<2)
/* mask enable for AUDN bit */
#define AK4113_MAN		(1<<1)
/* mask enable for PAR bit */
#define AK4113_MPR		(1<<0)

/* AK4113_REG_DATDTS */
/* DAT Start ID Counter */
#define AK4113_DCNT		(1<<4)
/* DTS-CD 16-bit Sync Word Detect */
#define AK4113_DTS16		(1<<3)
/* DTS-CD 14-bit Sync Word Detect */
#define AK4113_DTS14		(1<<2)
/* mask enable for DAT bit (if 1, no INT1 effect */
#define AK4113_MDAT1		(1<<1)
/* mask enable for DAT bit (if 1, no INT0 effect */
#define AK4113_MDAT0		(1<<0)

/* AK4113_REG_RCS0 */
/* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
#define AK4113_QINT		(1<<7)
/* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
#define AK4113_AUTO		(1<<6)
/* channel status buffer interrupt, 0 = no change, 1 = change */
#define AK4113_CINT		(1<<5)
/* PLL lock status, 0 = lock, 1 = unlock */
#define AK4113_UNLCK		(1<<4)
/* Validity bit, 0 = valid, 1 = invalid */
#define AK4113_V		(1<<3)
/* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
#define AK4113_STC		(1<<2)
/* audio bit output, 0 = audio, 1 = non-audio */
#define AK4113_AUDION		(1<<1)
/* parity error or biphase error status, 0 = no error, 1 = error */
#define AK4113_PAR		(1<<0)

/* AK4113_REG_RCS1 */
/* sampling frequency detection */
#define AK4113_FS3		(1<<7)
#define AK4113_FS2		(1<<6)
#define AK4113_FS1		(1<<5)
#define AK4113_FS0		(1<<4)
/* Pre-emphasis detect, 0 = OFF, 1 = ON */
#define AK4113_PEM		(1<<3)
/* DAT Start ID Detect, 0 = no detect, 1 = detect */
#define AK4113_DAT		(1<<2)
/* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
#define AK4113_DTSCD		(1<<1)
/* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
#define AK4113_NPCM		(1<<0)
#define AK4113_FS_8000HZ	(AK4113_FS3|AK4113_FS0)
#define AK4113_FS_11025HZ	(AK4113_FS2|AK4113_FS0)
#define AK4113_FS_16000HZ	(AK4113_FS2|AK4113_FS1|AK4113_FS0)
#define AK4113_FS_22050HZ	(AK4113_FS2)
#define AK4113_FS_24000HZ	(AK4113_FS2|AK4113_FS1)
#define AK4113_FS_32000HZ	(AK4113_FS1|AK4113_FS0)
#define AK4113_FS_44100HZ	(0)
#define AK4113_FS_48000HZ	(AK4113_FS1)
#define AK4113_FS_64000HZ	(AK4113_FS3|AK4113_FS1|AK4113_FS0)
#define AK4113_FS_88200HZ	(AK4113_FS3)
#define AK4113_FS_96000HZ	(AK4113_FS3|AK4113_FS1)
#define AK4113_FS_176400HZ	(AK4113_FS3|AK4113_FS2)
#define AK4113_FS_192000HZ	(AK4113_FS3|AK4113_FS2|AK4113_FS1)

/* AK4113_REG_RCS2 */
/* CRC for Q-subcode, 0 = no error, 1 = error */
#define AK4113_QCRC		(1<<1)
/* CRC for channel status, 0 = no error, 1 = error */
#define AK4113_CCRC		(1<<0)

/* flags for snd_ak4113_check_rate_and_errors() */
#define AK4113_CHECK_NO_STAT	(1<<0)	/* no statistics */
#define AK4113_CHECK_NO_RATE	(1<<1)	/* no rate check */

#define AK4113_CONTROLS		13

typedef void (ak4113_write_t)(void *private_data, unsigned char addr,
		unsigned char data);
typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr);

enum {
	AK4113_PARITY_ERRORS,
	AK4113_V_BIT_ERRORS,
	AK4113_QCRC_ERRORS,
	AK4113_CCRC_ERRORS,
	AK4113_NUM_ERRORS
};

struct ak4113 {
	struct snd_card *card;
	ak4113_write_t *write;
	ak4113_read_t *read;
	void *private_data;
	atomic_t wq_processing;
	struct mutex reinit_mutex;
	spinlock_t lock;
	unsigned char regmap[AK4113_WRITABLE_REGS];
	struct snd_kcontrol *kctls[AK4113_CONTROLS];
	struct snd_pcm_substream *substream;
	unsigned long errors[AK4113_NUM_ERRORS];
	unsigned char rcs0;
	unsigned char rcs1;
	unsigned char rcs2;
	struct delayed_work work;
	unsigned int check_flags;
	void *change_callback_private;
	void (*change_callback)(struct ak4113 *ak4113, unsigned char c0,
			unsigned char c1);
};

int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read,
		ak4113_write_t *write,
		const unsigned char *pgm,
		void *private_data, struct ak4113 **r_ak4113);
void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg,
		unsigned char mask, unsigned char val);
void snd_ak4113_reinit(struct ak4113 *ak4113);
int snd_ak4113_build(struct ak4113 *ak4113,
		struct snd_pcm_substream *capture_substream);
int snd_ak4113_external_rate(struct ak4113 *ak4113);
int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags);

#ifdef CONFIG_PM
void snd_ak4113_suspend(struct ak4113 *chip);
void snd_ak4113_resume(struct ak4113 *chip);
#else
static inline void snd_ak4113_suspend(struct ak4113 *chip) {}
static inline void snd_ak4113_resume(struct ak4113 *chip) {}
#endif

#endif /* __SOUND_AK4113_H */

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