FM / sound

/usr/src/linux-headers-5.15.0-181/include/sound/

/usr/src/linux-headers-5.15.0-181/include/sound

Name	Size	Mode	Actions
ac97/	-	0755	rm
sof/	-	0755	rm
ac97_codec.h	16044	0644	edit dl rm
aci.h	2458	0644	edit dl rm
ad1816a.h	4843	0644	edit dl rm
ad1843.h	1516	0644	edit dl rm
adau1373.h	706	0644	edit dl rm
ak4xxx-adda.h	2724	0644	edit dl rm
ak4113.h	10461	0644	edit dl rm
ak4114.h	9773	0644	edit dl rm
ak4117.h	8542	0644	edit dl rm
ak4531_codec.h	2478	0644	edit dl rm
ak4641.h	476	0644	edit dl rm
alc5623.h	536	0644	edit dl rm
asequencer.h	2975	0644	edit dl rm
asound.h	590	0644	edit dl rm
asoundef.h	16403	0644	edit dl rm
compress_driver.h	7986	0644	edit dl rm
control.h	9958	0644	edit dl rm
core.h	15895	0644	edit dl rm
cs35l33.h	888	0644	edit dl rm
cs35l34.h	741	0644	edit dl rm
cs35l35.h	2267	0644	edit dl rm
cs35l36.h	772	0644	edit dl rm
cs35l41.h	30889	0644	edit dl rm
cs42l42.h	35149	0644	edit dl rm
cs42l52.h	592	0644	edit dl rm
cs42l56.h	1046	0644	edit dl rm
cs42l73.h	361	0644	edit dl rm
cs4231-regs.h	7785	0644	edit dl rm
cs4271.h	961	0644	edit dl rm
cs8403.h	8138	0644	edit dl rm
cs8427.h	9954	0644	edit dl rm
da7213.h	1032	0644	edit dl rm
da7218.h	2468	0644	edit dl rm
da7219-aad.h	2263	0644	edit dl rm
da7219.h	998	0644	edit dl rm
da9055.h	707	0644	edit dl rm
designware_i2s.h	1631	0644	edit dl rm
dmaengine_pcm.h	6913	0644	edit dl rm
emu10k1.h	90722	0644	edit dl rm
emu10k1_synth.h	693	0644	edit dl rm
emu8000.h	3333	0644	edit dl rm
emu8000_reg.h	9767	0644	edit dl rm
emux_legacy.h	4811	0644	edit dl rm
emux_synth.h	6948	0644	edit dl rm
es1688.h	2923	0644	edit dl rm
graph_card.h	271	0644	edit dl rm
gus.h	20119	0644	edit dl rm
hdaudio.h	21538	0644	edit dl rm
hdaudio_ext.h	5680	0644	edit dl rm
hda_chmap.h	2660	0644	edit dl rm
hda_codec.h	17669	0644	edit dl rm
hda_component.h	2085	0644	edit dl rm
hda_hwdep.h	736	0644	edit dl rm
hda_i915.h	589	0644	edit dl rm
hda_register.h	10655	0644	edit dl rm
hda_regmap.h	6934	0644	edit dl rm
hda_verbs.h	17296	0644	edit dl rm
hdmi-codec.h	3011	0644	edit dl rm
hwdep.h	1925	0644	edit dl rm
i2c.h	2857	0644	edit dl rm
info.h	8053	0644	edit dl rm
initval.h	2484	0644	edit dl rm
intel-dsp-config.h	869	0644	edit dl rm
intel-nhlt.h	2851	0644	edit dl rm
jack.h	3172	0644	edit dl rm
l3.h	524	0644	edit dl rm
madera-pdata.h	1996	0644	edit dl rm
max9768.h	729	0644	edit dl rm
max98088.h	1074	0644	edit dl rm
max98090.h	534	0644	edit dl rm
max98095.h	1357	0644	edit dl rm
memalloc.h	2642	0644	edit dl rm
minors.h	3738	0644	edit dl rm
mixer_oss.h	1773	0644	edit dl rm
mpu401.h	3905	0644	edit dl rm
omap-hdmi-audio.h	971	0644	edit dl rm
opl3.h	11909	0644	edit dl rm
opl4.h	459	0644	edit dl rm
pcm-indirect.h	5159	0644	edit dl rm
pcm.h	53684	0644	edit dl rm
pcm_drm_eld.h	183	0644	edit dl rm
pcm_iec958.h	597	0644	edit dl rm
pcm_oss.h	2063	0644	edit dl rm
pcm_params.h	8864	0644	edit dl rm
pt2258.h	513	0644	edit dl rm
pxa2xx-lib.h	2190	0644	edit dl rm
rawmidi.h	5881	0644	edit dl rm
rt286.h	314	0644	edit dl rm
rt298.h	373	0644	edit dl rm
rt1015.h	283	0644	edit dl rm
rt5514.h	399	0644	edit dl rm
rt5659.h	880	0644	edit dl rm
rt5660.h	578	0644	edit dl rm
rt5663.h	476	0644	edit dl rm
rt5665.h	761	0644	edit dl rm
rt5668.h	646	0644	edit dl rm
rt5682.h	901	0644	edit dl rm
s3c24xx_uda134x.h	229	0644	edit dl rm
sb.h	10550	0644	edit dl rm
sb16_csp.h	2100	0644	edit dl rm
seq_device.h	2165	0644	edit dl rm
seq_kernel.h	3378	0644	edit dl rm
seq_midi_emul.h	6757	0644	edit dl rm
seq_midi_event.h	1356	0644	edit dl rm
seq_oss.h	2264	0644	edit dl rm
seq_oss_legacy.h	360	0644	edit dl rm
seq_virmidi.h	2123	0644	edit dl rm
sh_dac_audio.h	441	0644	edit dl rm
sh_fsi.h	693	0644	edit dl rm
simple_card.h	529	0644	edit dl rm
simple_card_utils.h	8351	0644	edit dl rm
snd_wavefront.h	5620	0644	edit dl rm
soc-acpi-intel-match.h	2074	0644	edit dl rm
soc-acpi.h	5637	0644	edit dl rm
soc-card.h	2944	0644	edit dl rm
soc-component.h	19387	0644	edit dl rm
soc-dai.h	19957	0644	edit dl rm
soc-dapm.h	32957	0644	edit dl rm
soc-dpcm.h	5523	0644	edit dl rm
soc-jack.h	3822	0644	edit dl rm
soc-link.h	1172	0644	edit dl rm
soc-topology.h	5835	0644	edit dl rm
soc.h	47899	0644	edit dl rm
sof.h	2596	0644	edit dl rm
soundfont.h	3903	0644	edit dl rm
spear_dma.h	350	0644	edit dl rm
spear_spdif.h	345	0644	edit dl rm
sta32x.h	1015	0644	edit dl rm
sta350.h	1474	0644	edit dl rm
tas2552-plat.h	283	0644	edit dl rm
tas5086.h	210	0644	edit dl rm
tea6330t.h	468	0644	edit dl rm
timer.h	5109	0644	edit dl rm
tlv.h	1627	0644	edit dl rm
tlv320aic3x.h	1777	0644	edit dl rm
tlv320aic32x4.h	1320	0644	edit dl rm
tlv320dac33-plat.h	574	0644	edit dl rm
tpa6130a2-plat.h	291	0644	edit dl rm
uda134x.h	451	0644	edit dl rm
uda1380.h	335	0644	edit dl rm
util_mem.h	1623	0644	edit dl rm
vx_core.h	15055	0644	edit dl rm
wavefront.h	18518	0644	edit dl rm
wm0010.h	466	0644	edit dl rm
wm1250-ev1.h	510	0644	edit dl rm
wm2000.h	479	0644	edit dl rm
wm2200.h	1353	0644	edit dl rm
wm5100.h	1129	0644	edit dl rm
wm8903.h	15377	0644	edit dl rm
wm8904.h	7389	0644	edit dl rm
wm8955.h	442	0644	edit dl rm
wm8960.h	888	0644	edit dl rm
wm8962.h	1694	0644	edit dl rm
wm8993.h	1076	0644	edit dl rm
wm8996.h	1289	0644	edit dl rm
wm9081.h	515	0644	edit dl rm
wm9090.h	634	0644	edit dl rm
wss.h	7949	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-181/include/sound/wm8903.h (15377B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * linux/sound/wm8903.h -- Platform data for WM8903
 *
 * Copyright 2010 Wolfson Microelectronics. PLC.
 */

#ifndef __LINUX_SND_WM8903_H
#define __LINUX_SND_WM8903_H

/*
 * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of
 * zero in platform data means "don't touch this pin".
 */
#define WM8903_GPIO_CONFIG_ZERO 0x8000

/*
 * R6 (0x06) - Mic Bias Control 0
 */
#define WM8903_MICDET_THR_MASK                  0x0030  /* MICDET_THR - [5:4] */
#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [5:4] */
#define WM8903_MICDET_THR_WIDTH                      2  /* MICDET_THR - [5:4] */
#define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
#define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
#define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
#define WM8903_MICDET_ENA                       0x0002  /* MICDET_ENA */
#define WM8903_MICDET_ENA_MASK                  0x0002  /* MICDET_ENA */
#define WM8903_MICDET_ENA_SHIFT                      1  /* MICDET_ENA */
#define WM8903_MICDET_ENA_WIDTH                      1  /* MICDET_ENA */
#define WM8903_MICBIAS_ENA                      0x0001  /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_MASK                 0x0001  /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_SHIFT                     0  /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_WIDTH                     1  /* MICBIAS_ENA */

/*
 * WM8903_GPn_FN values
 *
 * See datasheets for list of valid values per pin
 */
#define WM8903_GPn_FN_GPIO_OUTPUT                    0
#define WM8903_GPn_FN_BCLK                           1
#define WM8903_GPn_FN_IRQ_OUTPT                      2
#define WM8903_GPn_FN_GPIO_INPUT                     3
#define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT         4
#define WM8903_GPn_FN_MICBIAS_SHORT_DETECT           5
#define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT             6
#define WM8903_GPn_FN_FLL_LOCK_OUTPUT                8
#define WM8903_GPn_FN_FLL_CLOCK_OUTPUT               9

/*
 * R116 (0x74) - GPIO Control 1
 */
#define WM8903_GP1_FN_MASK                      0x1F00  /* GP1_FN - [12:8] */
#define WM8903_GP1_FN_SHIFT                          8  /* GP1_FN - [12:8] */
#define WM8903_GP1_FN_WIDTH                          5  /* GP1_FN - [12:8] */
#define WM8903_GP1_DIR                          0x0080  /* GP1_DIR */
#define WM8903_GP1_DIR_MASK                     0x0080  /* GP1_DIR */
#define WM8903_GP1_DIR_SHIFT                         7  /* GP1_DIR */
#define WM8903_GP1_DIR_WIDTH                         1  /* GP1_DIR */
#define WM8903_GP1_OP_CFG                       0x0040  /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_MASK                  0x0040  /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_SHIFT                      6  /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
#define WM8903_GP1_IP_CFG                       0x0020  /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_MASK                  0x0020  /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_SHIFT                      5  /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_WIDTH                      1  /* GP1_IP_CFG */
#define WM8903_GP1_LVL                          0x0010  /* GP1_LVL */
#define WM8903_GP1_LVL_MASK                     0x0010  /* GP1_LVL */
#define WM8903_GP1_LVL_SHIFT                         4  /* GP1_LVL */
#define WM8903_GP1_LVL_WIDTH                         1  /* GP1_LVL */
#define WM8903_GP1_PD                           0x0008  /* GP1_PD */
#define WM8903_GP1_PD_MASK                      0x0008  /* GP1_PD */
#define WM8903_GP1_PD_SHIFT                          3  /* GP1_PD */
#define WM8903_GP1_PD_WIDTH                          1  /* GP1_PD */
#define WM8903_GP1_PU                           0x0004  /* GP1_PU */
#define WM8903_GP1_PU_MASK                      0x0004  /* GP1_PU */
#define WM8903_GP1_PU_SHIFT                          2  /* GP1_PU */
#define WM8903_GP1_PU_WIDTH                          1  /* GP1_PU */
#define WM8903_GP1_INTMODE                      0x0002  /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_MASK                 0x0002  /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_SHIFT                     1  /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_WIDTH                     1  /* GP1_INTMODE */
#define WM8903_GP1_DB                           0x0001  /* GP1_DB */
#define WM8903_GP1_DB_MASK                      0x0001  /* GP1_DB */
#define WM8903_GP1_DB_SHIFT                          0  /* GP1_DB */
#define WM8903_GP1_DB_WIDTH                          1  /* GP1_DB */

/*
 * R117 (0x75) - GPIO Control 2
 */
#define WM8903_GP2_FN_MASK                      0x1F00  /* GP2_FN - [12:8] */
#define WM8903_GP2_FN_SHIFT                          8  /* GP2_FN - [12:8] */
#define WM8903_GP2_FN_WIDTH                          5  /* GP2_FN - [12:8] */
#define WM8903_GP2_DIR                          0x0080  /* GP2_DIR */
#define WM8903_GP2_DIR_MASK                     0x0080  /* GP2_DIR */
#define WM8903_GP2_DIR_SHIFT                         7  /* GP2_DIR */
#define WM8903_GP2_DIR_WIDTH                         1  /* GP2_DIR */
#define WM8903_GP2_OP_CFG                       0x0040  /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_MASK                  0x0040  /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_SHIFT                      6  /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
#define WM8903_GP2_IP_CFG                       0x0020  /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_MASK                  0x0020  /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_SHIFT                      5  /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_WIDTH                      1  /* GP2_IP_CFG */
#define WM8903_GP2_LVL                          0x0010  /* GP2_LVL */
#define WM8903_GP2_LVL_MASK                     0x0010  /* GP2_LVL */
#define WM8903_GP2_LVL_SHIFT                         4  /* GP2_LVL */
#define WM8903_GP2_LVL_WIDTH                         1  /* GP2_LVL */
#define WM8903_GP2_PD                           0x0008  /* GP2_PD */
#define WM8903_GP2_PD_MASK                      0x0008  /* GP2_PD */
#define WM8903_GP2_PD_SHIFT                          3  /* GP2_PD */
#define WM8903_GP2_PD_WIDTH                          1  /* GP2_PD */
#define WM8903_GP2_PU                           0x0004  /* GP2_PU */
#define WM8903_GP2_PU_MASK                      0x0004  /* GP2_PU */
#define WM8903_GP2_PU_SHIFT                          2  /* GP2_PU */
#define WM8903_GP2_PU_WIDTH                          1  /* GP2_PU */
#define WM8903_GP2_INTMODE                      0x0002  /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_MASK                 0x0002  /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_SHIFT                     1  /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_WIDTH                     1  /* GP2_INTMODE */
#define WM8903_GP2_DB                           0x0001  /* GP2_DB */
#define WM8903_GP2_DB_MASK                      0x0001  /* GP2_DB */
#define WM8903_GP2_DB_SHIFT                          0  /* GP2_DB */
#define WM8903_GP2_DB_WIDTH                          1  /* GP2_DB */

/*
 * R118 (0x76) - GPIO Control 3
 */
#define WM8903_GP3_FN_MASK                      0x1F00  /* GP3_FN - [12:8] */
#define WM8903_GP3_FN_SHIFT                          8  /* GP3_FN - [12:8] */
#define WM8903_GP3_FN_WIDTH                          5  /* GP3_FN - [12:8] */
#define WM8903_GP3_DIR                          0x0080  /* GP3_DIR */
#define WM8903_GP3_DIR_MASK                     0x0080  /* GP3_DIR */
#define WM8903_GP3_DIR_SHIFT                         7  /* GP3_DIR */
#define WM8903_GP3_DIR_WIDTH                         1  /* GP3_DIR */
#define WM8903_GP3_OP_CFG                       0x0040  /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_MASK                  0x0040  /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_SHIFT                      6  /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
#define WM8903_GP3_IP_CFG                       0x0020  /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_MASK                  0x0020  /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_SHIFT                      5  /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_WIDTH                      1  /* GP3_IP_CFG */
#define WM8903_GP3_LVL                          0x0010  /* GP3_LVL */
#define WM8903_GP3_LVL_MASK                     0x0010  /* GP3_LVL */
#define WM8903_GP3_LVL_SHIFT                         4  /* GP3_LVL */
#define WM8903_GP3_LVL_WIDTH                         1  /* GP3_LVL */
#define WM8903_GP3_PD                           0x0008  /* GP3_PD */
#define WM8903_GP3_PD_MASK                      0x0008  /* GP3_PD */
#define WM8903_GP3_PD_SHIFT                          3  /* GP3_PD */
#define WM8903_GP3_PD_WIDTH                          1  /* GP3_PD */
#define WM8903_GP3_PU                           0x0004  /* GP3_PU */
#define WM8903_GP3_PU_MASK                      0x0004  /* GP3_PU */
#define WM8903_GP3_PU_SHIFT                          2  /* GP3_PU */
#define WM8903_GP3_PU_WIDTH                          1  /* GP3_PU */
#define WM8903_GP3_INTMODE                      0x0002  /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_MASK                 0x0002  /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_SHIFT                     1  /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_WIDTH                     1  /* GP3_INTMODE */
#define WM8903_GP3_DB                           0x0001  /* GP3_DB */
#define WM8903_GP3_DB_MASK                      0x0001  /* GP3_DB */
#define WM8903_GP3_DB_SHIFT                          0  /* GP3_DB */
#define WM8903_GP3_DB_WIDTH                          1  /* GP3_DB */

/*
 * R119 (0x77) - GPIO Control 4
 */
#define WM8903_GP4_FN_MASK                      0x1F00  /* GP4_FN - [12:8] */
#define WM8903_GP4_FN_SHIFT                          8  /* GP4_FN - [12:8] */
#define WM8903_GP4_FN_WIDTH                          5  /* GP4_FN - [12:8] */
#define WM8903_GP4_DIR                          0x0080  /* GP4_DIR */
#define WM8903_GP4_DIR_MASK                     0x0080  /* GP4_DIR */
#define WM8903_GP4_DIR_SHIFT                         7  /* GP4_DIR */
#define WM8903_GP4_DIR_WIDTH                         1  /* GP4_DIR */
#define WM8903_GP4_OP_CFG                       0x0040  /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_MASK                  0x0040  /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_SHIFT                      6  /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
#define WM8903_GP4_IP_CFG                       0x0020  /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_MASK                  0x0020  /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_SHIFT                      5  /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_WIDTH                      1  /* GP4_IP_CFG */
#define WM8903_GP4_LVL                          0x0010  /* GP4_LVL */
#define WM8903_GP4_LVL_MASK                     0x0010  /* GP4_LVL */
#define WM8903_GP4_LVL_SHIFT                         4  /* GP4_LVL */
#define WM8903_GP4_LVL_WIDTH                         1  /* GP4_LVL */
#define WM8903_GP4_PD                           0x0008  /* GP4_PD */
#define WM8903_GP4_PD_MASK                      0x0008  /* GP4_PD */
#define WM8903_GP4_PD_SHIFT                          3  /* GP4_PD */
#define WM8903_GP4_PD_WIDTH                          1  /* GP4_PD */
#define WM8903_GP4_PU                           0x0004  /* GP4_PU */
#define WM8903_GP4_PU_MASK                      0x0004  /* GP4_PU */
#define WM8903_GP4_PU_SHIFT                          2  /* GP4_PU */
#define WM8903_GP4_PU_WIDTH                          1  /* GP4_PU */
#define WM8903_GP4_INTMODE                      0x0002  /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_MASK                 0x0002  /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_SHIFT                     1  /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_WIDTH                     1  /* GP4_INTMODE */
#define WM8903_GP4_DB                           0x0001  /* GP4_DB */
#define WM8903_GP4_DB_MASK                      0x0001  /* GP4_DB */
#define WM8903_GP4_DB_SHIFT                          0  /* GP4_DB */
#define WM8903_GP4_DB_WIDTH                          1  /* GP4_DB */

/*
 * R120 (0x78) - GPIO Control 5
 */
#define WM8903_GP5_FN_MASK                      0x1F00  /* GP5_FN - [12:8] */
#define WM8903_GP5_FN_SHIFT                          8  /* GP5_FN - [12:8] */
#define WM8903_GP5_FN_WIDTH                          5  /* GP5_FN - [12:8] */
#define WM8903_GP5_DIR                          0x0080  /* GP5_DIR */
#define WM8903_GP5_DIR_MASK                     0x0080  /* GP5_DIR */
#define WM8903_GP5_DIR_SHIFT                         7  /* GP5_DIR */
#define WM8903_GP5_DIR_WIDTH                         1  /* GP5_DIR */
#define WM8903_GP5_OP_CFG                       0x0040  /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_MASK                  0x0040  /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_SHIFT                      6  /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
#define WM8903_GP5_IP_CFG                       0x0020  /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_MASK                  0x0020  /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_SHIFT                      5  /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_WIDTH                      1  /* GP5_IP_CFG */
#define WM8903_GP5_LVL                          0x0010  /* GP5_LVL */
#define WM8903_GP5_LVL_MASK                     0x0010  /* GP5_LVL */
#define WM8903_GP5_LVL_SHIFT                         4  /* GP5_LVL */
#define WM8903_GP5_LVL_WIDTH                         1  /* GP5_LVL */
#define WM8903_GP5_PD                           0x0008  /* GP5_PD */
#define WM8903_GP5_PD_MASK                      0x0008  /* GP5_PD */
#define WM8903_GP5_PD_SHIFT                          3  /* GP5_PD */
#define WM8903_GP5_PD_WIDTH                          1  /* GP5_PD */
#define WM8903_GP5_PU                           0x0004  /* GP5_PU */
#define WM8903_GP5_PU_MASK                      0x0004  /* GP5_PU */
#define WM8903_GP5_PU_SHIFT                          2  /* GP5_PU */
#define WM8903_GP5_PU_WIDTH                          1  /* GP5_PU */
#define WM8903_GP5_INTMODE                      0x0002  /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_MASK                 0x0002  /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_SHIFT                     1  /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_WIDTH                     1  /* GP5_INTMODE */
#define WM8903_GP5_DB                           0x0001  /* GP5_DB */
#define WM8903_GP5_DB_MASK                      0x0001  /* GP5_DB */
#define WM8903_GP5_DB_SHIFT                          0  /* GP5_DB */
#define WM8903_GP5_DB_WIDTH                          1  /* GP5_DB */

#define WM8903_NUM_GPIO 5

struct wm8903_platform_data {
	bool irq_active_low;   /* Set if IRQ active low, default high */

/* Default register value for R6 (Mic bias), used to configure
	 * microphone detection.  In conjunction with gpio_cfg this
	 * can be used to route the microphone status signals out onto
	 * the GPIOs for use with snd_soc_jack_add_gpios().
	 */
	u16 micdet_cfg;

int micdet_delay;      /* Delay after microphone detection (ms) */

int gpio_base;
	u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */
};

#endif

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