/
usr
/
src
/
linux-headers-5.15.0-181
/
include
/
uapi
/
linux
/
/usr/src/linux-headers-5.15.0-181/include/uapi/linux
mkdir
upload
Name
Size
Mode
Actions
android/
-
0755
rm
byteorder/
-
0755
rm
caif/
-
0755
rm
can/
-
0755
rm
cifs/
-
0755
rm
dvb/
-
0755
rm
genwqe/
-
0755
rm
hdlc/
-
0755
rm
hsi/
-
0755
rm
iio/
-
0755
rm
isdn/
-
0755
rm
misc/
-
0755
rm
mmc/
-
0755
rm
netfilter/
-
0755
rm
netfilter_arp/
-
0755
rm
netfilter_bridge/
-
0755
rm
netfilter_ipv4/
-
0755
rm
netfilter_ipv6/
-
0755
rm
nfsd/
-
0755
rm
raid/
-
0755
rm
sched/
-
0755
rm
spi/
-
0755
rm
sunrpc/
-
0755
rm
surface_aggregator/
-
0755
rm
tc_act/
-
0755
rm
tc_ematch/
-
0755
rm
usb/
-
0755
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a.out.h
6959
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dl
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acct.h
4013
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dl
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acrn.h
16705
0644
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dl
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adb.h
1155
0644
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dl
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adfs_fs.h
1008
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dl
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affs_hardblocks.h
1578
0644
edit
dl
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agpgart.h
4001
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dl
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aio_abi.h
3398
0644
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dl
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am437x-vpfe.h
3681
0644
edit
dl
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apm_bios.h
3698
0644
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dl
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arcfb.h
213
0644
edit
dl
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arm_sdei.h
2766
0644
edit
dl
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aspeed-lpc-ctrl.h
1795
0644
edit
dl
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aspeed-p2a-ctrl.h
1921
0644
edit
dl
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atalk.h
1038
0644
edit
dl
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atm.h
7937
0644
edit
dl
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atmapi.h
952
0644
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dl
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atmarp.h
1296
0644
edit
dl
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atmbr2684.h
3271
0644
edit
dl
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atmclip.h
576
0644
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dl
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atmdev.h
7699
0644
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dl
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atmioc.h
1647
0644
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dl
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atmlec.h
2381
0644
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dl
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atmmpc.h
4226
0644
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dl
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atmppp.h
639
0644
edit
dl
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atmsap.h
4970
0644
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dl
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atmsvc.h
1853
0644
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dl
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atm_eni.h
648
0644
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dl
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atm_he.h
406
0644
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dl
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atm_idt77105.h
955
0644
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dl
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atm_nicstar.h
1278
0644
edit
dl
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atm_tcp.h
1637
0644
edit
dl
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atm_zatm.h
1540
0644
edit
dl
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audit.h
21267
0644
edit
dl
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aufs_type.h
12641
0644
edit
dl
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auto_dev-ioctl.h
4996
0644
edit
dl
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auto_fs.h
6450
0644
edit
dl
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auto_fs4.h
466
0644
edit
dl
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auxvec.h
1612
0644
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dl
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ax25.h
2824
0644
edit
dl
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batadv_packet.h
20360
0644
edit
dl
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batman_adv.h
16902
0644
edit
dl
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baycom.h
883
0644
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dl
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bcache.h
9910
0644
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dl
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bcm933xx_hcs.h
419
0644
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dl
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bfs_fs.h
1905
0644
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dl
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binfmts.h
791
0644
edit
dl
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blkpg.h
953
0644
edit
dl
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blktrace_api.h
4716
0644
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dl
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blkzoned.h
6508
0644
edit
dl
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bpf.h
235084
0644
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dl
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bpfilter.h
480
0644
edit
dl
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bpf_common.h
1382
0644
edit
dl
rm
bpf_perf_event.h
544
0644
edit
dl
rm
bpqether.h
981
0644
edit
dl
rm
bsg.h
2509
0644
edit
dl
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bt-bmc.h
587
0644
edit
dl
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btf.h
4811
0644
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dl
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btrfs.h
30904
0644
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dl
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btrfs_tree.h
27392
0644
edit
dl
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can.h
9268
0644
edit
dl
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capability.h
13547
0644
edit
dl
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capi.h
3157
0644
edit
dl
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cciss_defs.h
3281
0644
edit
dl
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cciss_ioctl.h
2790
0644
edit
dl
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ccs.h
767
0644
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dl
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cdrom.h
28949
0644
edit
dl
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cec-funcs.h
53453
0644
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dl
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cec.h
41334
0644
edit
dl
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cfm_bridge.h
1466
0644
edit
dl
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cgroupstats.h
2219
0644
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dl
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chio.h
5304
0644
edit
dl
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close_range.h
392
0644
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dl
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cm4000_cs.h
1821
0644
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dl
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cn_proc.h
3471
0644
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dl
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coda.h
18393
0644
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dl
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coff.h
12564
0644
edit
dl
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connector.h
2268
0644
edit
dl
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const.h
1006
0644
edit
dl
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coresight-stm.h
747
0644
edit
dl
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cramfs_fs.h
3570
0644
edit
dl
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cryptouser.h
5336
0644
edit
dl
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cuda.h
920
0644
edit
dl
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cxl_mem.h
6489
0644
edit
dl
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cyclades.h
984
0644
edit
dl
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cycx_cfm.h
2990
0644
edit
dl
rm
dcbnl.h
25292
0644
edit
dl
rm
dccp.h
6447
0644
edit
dl
rm
devlink.h
20207
0644
edit
dl
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dlm.h
2568
0644
edit
dl
rm
dlmconstants.h
5080
0644
edit
dl
rm
dlm_device.h
2599
0644
edit
dl
rm
dlm_netlink.h
1159
0644
edit
dl
rm
dlm_plock.h
909
0644
edit
dl
rm
dm-ioctl.h
11602
0644
edit
dl
rm
dm-log-userspace.h
15191
0644
edit
dl
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dma-buf.h
3779
0644
edit
dl
rm
dma-heap.h
1409
0644
edit
dl
rm
dns_resolver.h
3904
0644
edit
dl
rm
dqblk_xfs.h
9388
0644
edit
dl
rm
edd.h
5619
0644
edit
dl
rm
efs_fs_sb.h
2227
0644
edit
dl
rm
elf-em.h
2586
0644
edit
dl
rm
elf-fdpic.h
1139
0644
edit
dl
rm
elf.h
14180
0644
edit
dl
rm
errno.h
23
0644
edit
dl
rm
errqueue.h
2066
0644
edit
dl
rm
erspan.h
1074
0644
edit
dl
rm
ethtool.h
82554
0644
edit
dl
rm
ethtool_netlink.h
23088
0644
edit
dl
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eventpoll.h
3056
0644
edit
dl
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f2fs.h
3316
0644
edit
dl
rm
fadvise.h
842
0644
edit
dl
rm
falloc.h
3599
0644
edit
dl
rm
fanotify.h
7495
0644
edit
dl
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fb.h
16518
0644
edit
dl
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fcntl.h
4266
0644
edit
dl
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fd.h
12166
0644
edit
dl
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fdreg.h
5364
0644
edit
dl
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fib_rules.h
2036
0644
edit
dl
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fiemap.h
2790
0644
edit
dl
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filter.h
2265
0644
edit
dl
rm
firewire-cdev.h
44240
0644
edit
dl
rm
firewire-constants.h
3231
0644
edit
dl
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fou.h
909
0644
edit
dl
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fpga-dfl.h
8743
0644
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dl
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fs.h
12411
0644
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dl
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fscrypt.h
6638
0644
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dl
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fsi.h
2270
0644
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dl
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fsl_hypervisor.h
7316
0644
edit
dl
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fsl_mc.h
749
0644
edit
dl
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fsmap.h
4385
0644
edit
dl
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fsverity.h
3293
0644
edit
dl
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fuse.h
23048
0644
edit
dl
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futex.h
5145
0644
edit
dl
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gameport.h
912
0644
edit
dl
rm
genetlink.h
2190
0644
edit
dl
rm
gen_stats.h
1526
0644
edit
dl
rm
gfs2_ondisk.h
14769
0644
edit
dl
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gpio.h
19783
0644
edit
dl
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gsmmux.h
1144
0644
edit
dl
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gtp.h
731
0644
edit
dl
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hash_info.h
986
0644
edit
dl
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hdlc.h
652
0644
edit
dl
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hdlcdrv.h
2923
0644
edit
dl
rm
hdreg.h
22945
0644
edit
dl
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hid.h
1916
0644
edit
dl
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hiddev.h
6360
0644
edit
dl
rm
hidraw.h
2008
0644
edit
dl
rm
hpet.h
785
0644
edit
dl
rm
hsr_netlink.h
1101
0644
edit
dl
rm
hw_breakpoint.h
757
0644
edit
dl
rm
hyperv.h
10583
0644
edit
dl
rm
i2c-dev.h
1931
0644
edit
dl
rm
i2c.h
6905
0644
edit
dl
rm
i2o-dev.h
11646
0644
edit
dl
rm
i8k.h
1528
0644
edit
dl
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icmp.h
4800
0644
edit
dl
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icmpv6.h
4284
0644
edit
dl
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idxd.h
7624
0644
edit
dl
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if.h
11015
0644
edit
dl
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ife.h
351
0644
edit
dl
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if_addr.h
1912
0644
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dl
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if_addrlabel.h
721
0644
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dl
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if_alg.h
1566
0644
edit
dl
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if_arcnet.h
3717
0644
edit
dl
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if_arp.h
6604
0644
edit
dl
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if_bonding.h
5145
0644
edit
dl
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if_bridge.h
19121
0644
edit
dl
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if_cablemodem.h
986
0644
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dl
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if_eql.h
1364
0644
edit
dl
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if_ether.h
8457
0644
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if_fc.h
1738
0644
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dl
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if_fddi.h
4384
0644
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dl
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if_hippi.h
4235
0644
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dl
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if_infiniband.h
1245
0644
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dl
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if_link.h
31760
0644
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dl
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if_ltalk.h
225
0644
edit
dl
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if_macsec.h
6490
0644
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dl
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if_packet.h
8147
0644
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dl
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if_phonet.h
439
0644
edit
dl
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if_plip.h
660
0644
edit
dl
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if_ppp.h
29
0644
edit
dl
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if_pppol2tp.h
3318
0644
edit
dl
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if_pppox.h
4804
0644
edit
dl
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if_slip.h
872
0644
edit
dl
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if_team.h
2615
0644
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dl
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if_tun.h
4113
0644
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dl
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if_tunnel.h
4858
0644
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dl
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if_vlan.h
1846
0644
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dl
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if_x25.h
881
0644
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dl
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if_xdp.h
3011
0644
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dl
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igmp.h
3079
0644
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dl
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ila.h
1261
0644
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dl
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in.h
10897
0644
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dl
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in6.h
7593
0644
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dl
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inet_diag.h
5032
0644
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dl
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inotify.h
3307
0644
edit
dl
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input-event-codes.h
28894
0644
edit
dl
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input.h
16030
0644
edit
dl
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in_route.h
936
0644
edit
dl
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ioam6.h
2399
0644
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dl
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ioam6_genl.h
960
0644
edit
dl
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ioam6_iptunnel.h
451
0644
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dl
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ioctl.h
163
0644
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dl
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iommu.h
12031
0644
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dl
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ioprio.h
1471
0644
edit
dl
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io_uring.h
9795
0644
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dl
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ip.h
4828
0644
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dl
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ip6_tunnel.h
1953
0644
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ipc.h
2123
0644
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ipmi.h
15112
0644
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dl
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ipmi_bmc.h
503
0644
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dl
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ipmi_msgdefs.h
3430
0644
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dl
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ipsec.h
947
0644
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dl
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ipu-isys.h
481
0644
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dl
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ipu-psys.h
3663
0644
edit
dl
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ipv6.h
4341
0644
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dl
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ipv6_route.h
1923
0644
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dl
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ip_vs.h
14135
0644
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dl
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irqnr.h
104
0644
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dl
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iso_fs.h
6485
0644
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dl
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isst_if.h
5404
0644
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dl
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ivtv.h
3063
0644
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ivtvfb.h
1241
0644
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dl
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jffs2.h
6815
0644
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dl
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joystick.h
3449
0644
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dl
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kcm.h
822
0644
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dl
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kcmp.h
537
0644
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dl
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kcov.h
1959
0644
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dl
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kd.h
6311
0644
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dl
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kdev_t.h
441
0644
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dl
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kernel-page-flags.h
915
0644
edit
dl
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kernel.h
209
0644
edit
dl
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kernelcapi.h
1034
0644
edit
dl
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kexec.h
1970
0644
edit
dl
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keyboard.h
13474
0644
edit
dl
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keyctl.h
6010
0644
edit
dl
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kfd_ioctl.h
24151
0644
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dl
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kvm.h
60796
0644
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dl
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kvm_para.h
1016
0644
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dl
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l2tp.h
5788
0644
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dl
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landlock.h
4915
0644
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dl
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libc-compat.h
8304
0644
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dl
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limits.h
947
0644
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dl
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lirc.h
8144
0644
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dl
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llc.h
3179
0644
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dl
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loop.h
3512
0644
edit
dl
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lp.h
4205
0644
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dl
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lwtunnel.h
2238
0644
edit
dl
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magic.h
3801
0644
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dl
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major.h
4657
0644
edit
dl
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map_to_7segment.h
6608
0644
edit
dl
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matroxfb.h
1464
0644
edit
dl
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max2175.h
1035
0644
edit
dl
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mctp.h
736
0644
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dl
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mdio.h
17283
0644
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dl
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media-bus-format.h
6909
0644
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dl
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media.h
13223
0644
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dl
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mei.h
3475
0644
edit
dl
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membarrier.h
9377
0644
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dl
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memfd.h
1339
0644
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dl
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mempolicy.h
2583
0644
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dl
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meye.h
2529
0644
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dl
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mii.h
9511
0644
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dl
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minix_fs.h
2122
0644
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dl
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mman.h
1599
0644
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dl
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mmtimer.h
2117
0644
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dl
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module.h
270
0644
edit
dl
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mount.h
5107
0644
edit
dl
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mpls.h
2317
0644
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dl
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mpls_iptunnel.h
776
0644
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dl
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mptcp.h
5750
0644
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dl
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mqueue.h
2201
0644
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dl
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mroute.h
5937
0644
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dl
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mroute6.h
4945
0644
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dl
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mrp_bridge.h
1718
0644
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dl
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msdos_fs.h
6746
0644
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dl
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msg.h
3401
0644
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dl
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mtio.h
8175
0644
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dl
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nbd-netlink.h
2423
0644
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dl
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nbd.h
3039
0644
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dl
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ncsi.h
4828
0644
edit
dl
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ndctl.h
6793
0644
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dl
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neighbour.h
5124
0644
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dl
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net.h
2100
0644
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dl
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netconf.h
629
0644
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dl
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netdevice.h
2268
0644
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dl
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netfilter.h
1780
0644
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dl
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netfilter_arp.h
471
0644
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dl
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netfilter_bridge.h
1209
0644
edit
dl
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netfilter_ipv4.h
1548
0644
edit
dl
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netfilter_ipv6.h
1443
0644
edit
dl
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netlink.h
11717
0644
edit
dl
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netlink_diag.h
1550
0644
edit
dl
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netrom.h
807
0644
edit
dl
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net_dropmon.h
2886
0644
edit
dl
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net_namespace.h
730
0644
edit
dl
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net_tstamp.h
5571
0644
edit
dl
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nexthop.h
2835
0644
edit
dl
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nfc.h
11236
0644
edit
dl
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nfs.h
4481
0644
edit
dl
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nfs2.h
1468
0644
edit
dl
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nfs3.h
2468
0644
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dl
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nfs4.h
6506
0644
edit
dl
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nfs4_mount.h
1953
0644
edit
dl
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nfsacl.h
733
0644
edit
dl
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nfs_fs.h
1656
0644
edit
dl
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nfs_idmap.h
2258
0644
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dl
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nfs_mount.h
2142
0644
edit
dl
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nilfs2_api.h
7565
0644
edit
dl
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nilfs2_ondisk.h
18053
0644
edit
dl
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nitro_enclaves.h
13167
0644
edit
dl
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nl80211-vnd-intel.h
2937
0644
edit
dl
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nl80211.h
314008
0644
edit
dl
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nsfs.h
639
0644
edit
dl
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nubus.h
8206
0644
edit
dl
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nvme_ioctl.h
1676
0644
edit
dl
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nvram.h
547
0644
edit
dl
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Edit:
/usr/src/linux-headers-5.15.0-181/include/uapi/linux/serial_reg.h
(15552B)
/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */ /* * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. * * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #ifndef _LINUX_SERIAL_REG_H #define _LINUX_SERIAL_REG_H /* * DLAB=0 */ #define UART_RX 0 /* In: Receive buffer */ #define UART_TX 0 /* Out: Transmit buffer */ #define UART_IER 1 /* Out: Interrupt Enable Register */ #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ /* * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 */ #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ #define UART_IIR 2 /* In: Interrupt ID Register */ #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ #define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ #define UART_IIR_MSI 0x00 /* Modem status interrupt */ #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ #define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ #define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ /* * Note: The FIFO trigger levels are chip specific: * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 * PC16550D: 1 4 8 14 xx xx xx xx * TI16C550A: 1 4 8 14 xx xx xx xx * TI16C550C: 1 4 8 14 xx xx xx xx * ST16C550: 1 4 8 14 xx xx xx xx * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 * NS16C552: 1 4 8 14 xx xx xx xx * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 * TI16C752: 8 16 56 60 8 16 32 56 * OX16C950: 16 32 112 120 16 32 64 112 PORT_16C950 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA */ #define UART_FCR_R_TRIG_00 0x00 #define UART_FCR_R_TRIG_01 0x40 #define UART_FCR_R_TRIG_10 0x80 #define UART_FCR_R_TRIG_11 0xc0 #define UART_FCR_T_TRIG_00 0x00 #define UART_FCR_T_TRIG_01 0x10 #define UART_FCR_T_TRIG_10 0x20 #define UART_FCR_T_TRIG_11 0x30 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ /* 16650 definitions */ #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750 and some Freescale UARTs) */ #define UART_FCR_R_TRIG_SHIFT 6 #define UART_FCR_R_TRIG_BITS(x) \ (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT) #define UART_FCR_R_TRIG_MAX_STATE 4 #define UART_LCR 3 /* Out: Line Control Register */ /* * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define UART_LCR_SBC 0x40 /* Set break control */ #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ #define UART_LCR_EPAR 0x10 /* Even parity select */ #define UART_LCR_PARITY 0x08 /* Parity Enable */ #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ /* * Access to some registers depends on register access / configuration * mode. */ #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ #define UART_MCR_RTS 0x02 /* RTS complement */ #define UART_MCR_DTR 0x01 /* DTR complement */ #define UART_LSR 5 /* In: Line Status Register */ #define UART_LSR_FIFOE 0x80 /* Fifo error */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ #define UART_LSR_FE 0x08 /* Frame error indicator */ #define UART_LSR_PE 0x04 /* Parity error indicator */ #define UART_LSR_OE 0x02 /* Overrun error indicator */ #define UART_LSR_DR 0x01 /* Receiver data ready */ #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ #define UART_MSR 6 /* In: Modem Status Register */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ #define UART_MSR_RI 0x40 /* Ring Indicator */ #define UART_MSR_DSR 0x20 /* Data Set Ready */ #define UART_MSR_CTS 0x10 /* Clear to Send */ #define UART_MSR_DDCD 0x08 /* Delta DCD */ #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ #define UART_MSR_DDSR 0x02 /* Delta DSR */ #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ #define UART_SCR 7 /* I/O: Scratch Register */ /* * DLAB=1 */ #define UART_DLL 0 /* Out: Divisor Latch Low */ #define UART_DLM 1 /* Out: Divisor Latch High */ #define UART_DIV_MAX 0xFFFF /* Max divisor value */ /* * LCR=0xBF (or DLAB=1 for 16C660) */ #define UART_EFR 2 /* I/O: Extended Features Register */ #define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */ #define UART_EFR_CTS 0x80 /* CTS flow control */ #define UART_EFR_RTS 0x40 /* RTS flow control */ #define UART_EFR_SCD 0x20 /* Special character detect */ #define UART_EFR_ECB 0x10 /* Enhanced control bit */ /* * the low four bits control software flow control */ /* * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 */ #define UART_XON1 4 /* I/O: Xon character 1 */ #define UART_XON2 5 /* I/O: Xon character 2 */ #define UART_XOFF1 6 /* I/O: Xoff character 1 */ #define UART_XOFF2 7 /* I/O: Xoff character 2 */ /* * EFR[4]=1 MCR[6]=1, TI16C752 */ #define UART_TI752_TCR 6 /* I/O: transmission control register */ #define UART_TI752_TLR 7 /* I/O: trigger level register */ /* * LCR=0xBF, XR16C85x */ #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx * In: Fifo count * Out: Fifo custom trigger levels */ /* * These are the definitions for the Programmable Trigger Register */ #define UART_TRG_1 0x01 #define UART_TRG_4 0x04 #define UART_TRG_8 0x08 #define UART_TRG_16 0x10 #define UART_TRG_32 0x20 #define UART_TRG_64 0x40 #define UART_TRG_96 0x60 #define UART_TRG_120 0x78 #define UART_TRG_128 0x80 #define UART_FCTR 1 /* Feature Control Register */ #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ #define UART_FCTR_RTS_4DELAY 0x01 #define UART_FCTR_RTS_6DELAY 0x02 #define UART_FCTR_RTS_8DELAY 0x03 #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ /* * LCR=0xBF, FCTR[6]=1 */ #define UART_EMSR 7 /* Extended Mode Select Register */ #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ /* * The Intel XScale on-chip UARTs define these bits */ #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ #define UART_IER_UUE 0x40 /* UART Unit Enable */ #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ /* * These register definitions are for the 16C950 */ #define UART_ASR 0x01 /* Additional Status Register */ #define UART_RFL 0x03 /* Receiver FIFO level */ #define UART_TFL 0x04 /* Transmitter FIFO level */ #define UART_ICR 0x05 /* Index Control Register */ /* The 16950 ICR registers */ #define UART_ACR 0x00 /* Additional Control Register */ #define UART_CPR 0x01 /* Clock Prescalar Register */ #define UART_TCR 0x02 /* Times Clock Register */ #define UART_CKS 0x03 /* Clock Select Register */ #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ #define UART_FCL 0x06 /* Flow Control Level Lower */ #define UART_FCH 0x07 /* Flow Control Level Higher */ #define UART_ID1 0x08 /* ID #1 */ #define UART_ID2 0x09 /* ID #2 */ #define UART_ID3 0x0A /* ID #3 */ #define UART_REV 0x0B /* Revision */ #define UART_CSR 0x0C /* Channel Software Reset */ #define UART_NMR 0x0D /* Nine-bit Mode Register */ #define UART_CTR 0xFF /* * The 16C950 Additional Control Register */ #define UART_ACR_RXDIS 0x01 /* Receiver disable */ #define UART_ACR_TXDIS 0x02 /* Transmitter disable */ #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ #define UART_ACR_ASREN 0x80 /* Additional status enable */ /* * These definitions are for the RSA-DV II/S card, from * * Kiyokazu SUTO <suto@ks-and-ks.ne.jp> */ #define UART_RSA_BASE (-8) #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ /* * The RSA DSV/II board has two fixed clock frequencies. One is the * standard rate, and the other is 8 times faster. */ #define SERIAL_RSA_BAUD_BASE (921600) #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) /* Extra registers for TI DA8xx/66AK2x */ #define UART_DA830_PWREMU_MGMT 12 /* PWREMU_MGMT register bits */ #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */ #define UART_DA830_PWREMU_MGMT_URRST (1 << 13) /* Receiver reset/enable */ #define UART_DA830_PWREMU_MGMT_UTRST (1 << 14) /* Transmitter reset/enable */ /* * Extra serial register definitions for the internal UARTs * in TI OMAP processors. */ #define OMAP1_UART1_BASE 0xfffb0000 #define OMAP1_UART2_BASE 0xfffb0800 #define OMAP1_UART3_BASE 0xfffb9800 #define UART_OMAP_MDR1 0x08 /* Mode definition register */ #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ #define UART_OMAP_SCR 0x10 /* Supplementary control register */ #define UART_OMAP_SSR 0x11 /* Supplementary status register */ #define UART_OMAP_EBLR 0x12 /* BOF length register */ #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ #define UART_OMAP_MVER 0x14 /* Module version register */ #define UART_OMAP_SYSC 0x15 /* System configuration register */ #define UART_OMAP_SYSS 0x16 /* System status register */ #define UART_OMAP_WER 0x17 /* Wake-up enable register */ #define UART_OMAP_TX_LVL 0x1a /* TX FIFO level register */ /* * These are the definitions for the MDR1 register */ #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ /* * These are definitions for the Altera ALTR_16550_F32/F64/F128 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs). */ #define UART_ALTR_AFR 0x40 /* Additional Features Register */ #define UART_ALTR_EN_TXFIFO_LW 0x01 /* Enable the TX FIFO Low Watermark */ #define UART_ALTR_TX_LOW 0x41 /* Tx FIFO Low Watermark */ #endif /* _LINUX_SERIAL_REG_H */
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