FM / asm

/usr/src/linux-headers-5.15.0-190/arch/arm/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/arm/include/asm

Name	Size	Mode	Actions
hardware/	-	0755	rm
mach/	-	0755	rm
vdso/	-	0755	rm
xen/	-	0755	rm
archrandom.h	192	0644	edit dl rm
arch_gicv3.h	6327	0644	edit dl rm
arch_timer.h	3124	0644	edit dl rm
arm-cci.h	535	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
assembler.h	13106	0644	edit dl rm
atomic.h	12536	0644	edit dl rm
auxvec.h	29	0644	edit dl rm
barrier.h	2910	0644	edit dl rm
bitops.h	7627	0644	edit dl rm
bitrev.h	451	0644	edit dl rm
bL_switcher.h	2186	0644	edit dl rm
bug.h	2620	0644	edit dl rm
bugs.h	297	0644	edit dl rm
cache.h	794	0644	edit dl rm
cacheflush.h	15794	0644	edit dl rm
cachetype.h	2779	0644	edit dl rm
checksum.h	4026	0644	edit dl rm
clocksource.h	161	0644	edit dl rm
cmpxchg.h	6328	0644	edit dl rm
compiler.h	978	0644	edit dl rm
cp15.h	3302	0644	edit dl rm
cpu.h	387	0644	edit dl rm
cpufeature.h	1291	0644	edit dl rm
cpuidle.h	1628	0644	edit dl rm
cputype.h	8766	0644	edit dl rm
cti.h	3703	0644	edit dl rm
dcc.h	623	0644	edit dl rm
delay.h	2903	0644	edit dl rm
device.h	636	0644	edit dl rm
div64.h	2640	0644	edit dl rm
dma-direct.h	1341	0644	edit dl rm
dma-iommu.h	908	0644	edit dl rm
dma-mapping.h	4714	0644	edit dl rm
dma.h	4287	0644	edit dl rm
dmi.h	378	0644	edit dl rm
domain.h	3751	0644	edit dl rm
ecard.h	6119	0644	edit dl rm
edac.h	995	0644	edit dl rm
efi.h	2501	0644	edit dl rm
elf.h	4636	0644	edit dl rm
entry-macro-multi.S	336	0644	edit dl rm
exception.h	416	0644	edit dl rm
fb.h	375	0644	edit dl rm
fiq.h	1391	0644	edit dl rm
firmware.h	1728	0644	edit dl rm
fixmap.h	1881	0644	edit dl rm
floppy.h	2318	0644	edit dl rm
fncpy.h	2552	0644	edit dl rm
fpstate.h	1478	0644	edit dl rm
ftrace.h	1821	0644	edit dl rm
futex.h	4357	0644	edit dl rm
glue-cache.h	3515	0644	edit dl rm
glue-df.h	2110	0644	edit dl rm
glue-pf.h	1005	0644	edit dl rm
glue-proc.h	4424	0644	edit dl rm
glue.h	613	0644	edit dl rm
gpio.h	615	0644	edit dl rm
hardirq.h	246	0644	edit dl rm
highmem.h	2379	0644	edit dl rm
hugetlb-3level.h	690	0644	edit dl rm
hugetlb.h	513	0644	edit dl rm
hwcap.h	378	0644	edit dl rm
hw_breakpoint.h	3811	0644	edit dl rm
hw_irq.h	349	0644	edit dl rm
hypervisor.h	224	0644	edit dl rm
ide.h	566	0644	edit dl rm
idmap.h	359	0644	edit dl rm
insn.h	636	0644	edit dl rm
io.h	15027	0644	edit dl rm
irq.h	887	0644	edit dl rm
irqflags.h	3969	0644	edit dl rm
irq_work.h	234	0644	edit dl rm
jump_label.h	1009	0644	edit dl rm
kasan.h	708	0644	edit dl rm
kasan_def.h	2726	0644	edit dl rm
Kbuild	186	0644	edit dl rm
kexec-internal.h	272	0644	edit dl rm
kexec.h	2255	0644	edit dl rm
kgdb.h	2783	0644	edit dl rm
kprobes.h	2248	0644	edit dl rm
krait-l2-accessors.h	231	0644	edit dl rm
linkage.h	216	0644	edit dl rm
mc146818rtc.h	720	0644	edit dl rm
mcpm.h	12061	0644	edit dl rm
mcs_spinlock.h	570	0644	edit dl rm
memblock.h	248	0644	edit dl rm
memory.h	10945	0644	edit dl rm
mmu.h	953	0644	edit dl rm
mmu_context.h	3461	0644	edit dl rm
module.h	1216	0644	edit dl rm
module.lds.h	134	0644	edit dl rm
mpu.h	3300	0644	edit dl rm
mtd-xip.h	520	0644	edit dl rm
neon.h	1041	0644	edit dl rm
nwflash.h	195	0644	edit dl rm
opcodes-sec.h	350	0644	edit dl rm
opcodes-virt.h	684	0644	edit dl rm
opcodes.h	8118	0644	edit dl rm
outercache.h	3268	0644	edit dl rm
page-nommu.h	811	0644	edit dl rm
page.h	3448	0644	edit dl rm
paravirt.h	477	0644	edit dl rm
patch.h	438	0644	edit dl rm
pci.h	794	0644	edit dl rm
percpu.h	1069	0644	edit dl rm
perf_event.h	708	0644	edit dl rm
pgalloc.h	3373	0644	edit dl rm
pgtable-2level-hwdef.h	3385	0644	edit dl rm
pgtable-2level-types.h	1278	0644	edit dl rm
pgtable-2level.h	8645	0644	edit dl rm
pgtable-3level-hwdef.h	3435	0644	edit dl rm
pgtable-3level-types.h	1331	0644	edit dl rm
pgtable-3level.h	8148	0644	edit dl rm
pgtable-hwdef.h	321	0644	edit dl rm
pgtable-nommu.h	1979	0644	edit dl rm
pgtable.h	10492	0644	edit dl rm
probes.h	1332	0644	edit dl rm
proc-fns.h	4754	0644	edit dl rm
processor.h	3166	0644	edit dl rm
procinfo.h	1152	0644	edit dl rm
prom.h	552	0644	edit dl rm
psci.h	379	0644	edit dl rm
ptdump.h	923	0644	edit dl rm
ptrace.h	4841	0644	edit dl rm
seccomp.h	281	0644	edit dl rm
sections.h	622	0644	edit dl rm
secure_cntvoff.h	152	0644	edit dl rm
setup.h	773	0644	edit dl rm
set_memory.h	720	0644	edit dl rm
shmparam.h	419	0644	edit dl rm
signal.h	559	0644	edit dl rm
smp.h	2839	0644	edit dl rm
smp_plat.h	2535	0644	edit dl rm
smp_scu.h	1352	0644	edit dl rm
smp_twd.h	590	0644	edit dl rm
sparsemem.h	716	0644	edit dl rm
spectre.h	906	0644	edit dl rm
spinlock.h	5645	0644	edit dl rm
spinlock_types.h	541	0644	edit dl rm
stackprotector.h	1357	0644	edit dl rm
stacktrace.h	742	0644	edit dl rm
string.h	2277	0644	edit dl rm
suspend.h	369	0644	edit dl rm
swab.h	1005	0644	edit dl rm
switch_to.h	1058	0644	edit dl rm
sync_bitops.h	1514	0644	edit dl rm
syscall.h	2347	0644	edit dl rm
system_info.h	763	0644	edit dl rm
system_misc.h	1005	0644	edit dl rm
tcm.h	925	0644	edit dl rm
therm.h	655	0644	edit dl rm
thread_info.h	4974	0644	edit dl rm
thread_notify.h	1086	0644	edit dl rm
timex.h	431	0644	edit dl rm
tlb.h	1442	0644	edit dl rm
tlbflush.h	17909	0644	edit dl rm
tls.h	3166	0644	edit dl rm
topology.h	1139	0644	edit dl rm
traps.h	911	0644	edit dl rm
uaccess-asm.h	2703	0644	edit dl rm
uaccess.h	17431	0644	edit dl rm
ucontext.h	2745	0644	edit dl rm
unified.h	979	0644	edit dl rm
unistd.h	1578	0644	edit dl rm
unwind.h	1173	0644	edit dl rm
uprobes.h	948	0644	edit dl rm
user.h	4302	0644	edit dl rm
v7m.h	3233	0644	edit dl rm
vdso.h	507	0644	edit dl rm
vdso_datapage.h	444	0644	edit dl rm
vermagic.h	800	0644	edit dl rm
vfp.h	2969	0644	edit dl rm
vfpmacros.h	2074	0644	edit dl rm
vga.h	305	0644	edit dl rm
virt.h	1855	0644	edit dl rm
vmalloc.h	87	0644	edit dl rm
vmlinux.lds.h	4490	0644	edit dl rm
word-at-a-time.h	2128	0644	edit dl rm
xor.h	5204	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/arm/include/asm/atomic.h (12536B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  arch/arm/include/asm/atomic.h
 *
 *  Copyright (C) 1996 Russell King.
 *  Copyright (C) 2002 Deep Blue Solutions Ltd.
 */
#ifndef __ASM_ARM_ATOMIC_H
#define __ASM_ARM_ATOMIC_H

#include <linux/compiler.h>
#include <linux/prefetch.h>
#include <linux/types.h>
#include <linux/irqflags.h>
#include <asm/barrier.h>
#include <asm/cmpxchg.h>

#ifdef __KERNEL__

/*
 * On ARM, ordinary assignment (str instruction) doesn't clear the local
 * strex/ldrex monitor on some implementations. The reason we can use it for
 * atomic_set() is the clrex or dummy strex done on every exception return.
 */
#define arch_atomic_read(v)	READ_ONCE((v)->counter)
#define arch_atomic_set(v,i)	WRITE_ONCE(((v)->counter), (i))

#if __LINUX_ARM_ARCH__ >= 6

/*
 * ARMv6 UP and SMP safe atomic ops.  We use load exclusive and
 * store exclusive to ensure that these are atomic.  We may loop
 * to ensure that the update happens.
 */

#define ATOMIC_OP(op, c_op, asm_op)					\
static inline void arch_atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long tmp;						\
	int result;							\
									\
	prefetchw(&v->counter);						\
	__asm__ __volatile__("@ atomic_" #op "\n"			\
"1:	ldrex	%0, [%3]\n"						\
"	" #asm_op "	%0, %0, %4\n"					\
"	strex	%1, %0, [%3]\n"						\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "Ir" (i)					\
	: "cc");							\
}									\

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v)	\
{									\
	unsigned long tmp;						\
	int result;							\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic_" #op "_return\n"		\
"1:	ldrex	%0, [%3]\n"						\
"	" #asm_op "	%0, %0, %4\n"					\
"	strex	%1, %0, [%3]\n"						\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "Ir" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v)	\
{									\
	unsigned long tmp;						\
	int result, val;						\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic_fetch_" #op "\n"			\
"1:	ldrex	%0, [%4]\n"						\
"	" #asm_op "	%1, %0, %5\n"					\
"	strex	%2, %1, [%4]\n"						\
"	teq	%2, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter)	\
	: "r" (&v->counter), "Ir" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define arch_atomic_add_return_relaxed		arch_atomic_add_return_relaxed
#define arch_atomic_sub_return_relaxed		arch_atomic_sub_return_relaxed
#define arch_atomic_fetch_add_relaxed		arch_atomic_fetch_add_relaxed
#define arch_atomic_fetch_sub_relaxed		arch_atomic_fetch_sub_relaxed

#define arch_atomic_fetch_and_relaxed		arch_atomic_fetch_and_relaxed
#define arch_atomic_fetch_andnot_relaxed	arch_atomic_fetch_andnot_relaxed
#define arch_atomic_fetch_or_relaxed		arch_atomic_fetch_or_relaxed
#define arch_atomic_fetch_xor_relaxed		arch_atomic_fetch_xor_relaxed

static inline int arch_atomic_cmpxchg_relaxed(atomic_t *ptr, int old, int new)
{
	int oldval;
	unsigned long res;

prefetchw(&ptr->counter);

do {
		__asm__ __volatile__("@ atomic_cmpxchg\n"
		"ldrex	%1, [%3]\n"
		"mov	%0, #0\n"
		"teq	%1, %4\n"
		"strexeq %0, %5, [%3]\n"
		    : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
		    : "r" (&ptr->counter), "Ir" (old), "r" (new)
		    : "cc");
	} while (res);

return oldval;
}
#define arch_atomic_cmpxchg_relaxed		arch_atomic_cmpxchg_relaxed

static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
{
	int oldval, newval;
	unsigned long tmp;

smp_mb();
	prefetchw(&v->counter);

__asm__ __volatile__ ("@ atomic_add_unless\n"
"1:	ldrex	%0, [%4]\n"
"	teq	%0, %5\n"
"	beq	2f\n"
"	add	%1, %0, %6\n"
"	strex	%2, %1, [%4]\n"
"	teq	%2, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (u), "r" (a)
	: "cc");

if (oldval != u)
		smp_mb();

return oldval;
}
#define arch_atomic_fetch_add_unless		arch_atomic_fetch_add_unless

#else /* ARM_ARCH_6 */

#ifdef CONFIG_SMP
#error SMP not supported on pre-ARMv6 CPUs
#endif

#define ATOMIC_OP(op, c_op, asm_op)					\
static inline void arch_atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long flags;						\
									\
	raw_local_irq_save(flags);					\
	v->counter c_op i;						\
	raw_local_irq_restore(flags);					\
}									\

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int arch_atomic_##op##_return(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	int val;							\
									\
	raw_local_irq_save(flags);					\
	v->counter c_op i;						\
	val = v->counter;						\
	raw_local_irq_restore(flags);					\
									\
	return val;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int arch_atomic_fetch_##op(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	int val;							\
									\
	raw_local_irq_save(flags);					\
	val = v->counter;						\
	v->counter c_op i;						\
	raw_local_irq_restore(flags);					\
									\
	return val;							\
}

static inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
{
	int ret;
	unsigned long flags;

raw_local_irq_save(flags);
	ret = v->counter;
	if (likely(ret == old))
		v->counter = new;
	raw_local_irq_restore(flags);

return ret;
}

#define arch_atomic_fetch_andnot		arch_atomic_fetch_andnot

#endif /* __LINUX_ARM_ARCH__ */

#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_OP_RETURN(op, c_op, asm_op)				\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(add, +=, add)
ATOMIC_OPS(sub, -=, sub)

#define arch_atomic_andnot arch_atomic_andnot

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(and, &=, and)
ATOMIC_OPS(andnot, &= ~, bic)
ATOMIC_OPS(or,  |=, orr)
ATOMIC_OPS(xor, ^=, eor)

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

#define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), new))

#ifndef CONFIG_GENERIC_ATOMIC64
typedef struct {
	s64 counter;
} atomic64_t;

#define ATOMIC64_INIT(i) { (i) }

#ifdef CONFIG_ARM_LPAE
static inline s64 arch_atomic64_read(const atomic64_t *v)
{
	s64 result;

__asm__ __volatile__("@ atomic64_read\n"
"	ldrd	%0, %H0, [%1]"
	: "=&r" (result)
	: "r" (&v->counter), "Qo" (v->counter)
	);

return result;
}

static inline void arch_atomic64_set(atomic64_t *v, s64 i)
{
	__asm__ __volatile__("@ atomic64_set\n"
"	strd	%2, %H2, [%1]"
	: "=Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	);
}
#else
static inline s64 arch_atomic64_read(const atomic64_t *v)
{
	s64 result;

__asm__ __volatile__("@ atomic64_read\n"
"	ldrexd	%0, %H0, [%1]"
	: "=&r" (result)
	: "r" (&v->counter), "Qo" (v->counter)
	);

return result;
}

static inline void arch_atomic64_set(atomic64_t *v, s64 i)
{
	s64 tmp;

prefetchw(&v->counter);
	__asm__ __volatile__("@ atomic64_set\n"
"1:	ldrexd	%0, %H0, [%2]\n"
"	strexd	%0, %3, %H3, [%2]\n"
"	teq	%0, #0\n"
"	bne	1b"
	: "=&r" (tmp), "=Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");
}
#endif

#define ATOMIC64_OP(op, op1, op2)					\
static inline void arch_atomic64_##op(s64 i, atomic64_t *v)		\
{									\
	s64 result;							\
	unsigned long tmp;						\
									\
	prefetchw(&v->counter);						\
	__asm__ __volatile__("@ atomic64_" #op "\n"			\
"1:	ldrexd	%0, %H0, [%3]\n"					\
"	" #op1 " %Q0, %Q0, %Q4\n"					\
"	" #op2 " %R0, %R0, %R4\n"					\
"	strexd	%1, %0, %H0, [%3]\n"					\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "r" (i)					\
	: "cc");							\
}									\

#define ATOMIC64_OP_RETURN(op, op1, op2)				\
static inline s64							\
arch_atomic64_##op##_return_relaxed(s64 i, atomic64_t *v)		\
{									\
	s64 result;							\
	unsigned long tmp;						\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic64_" #op "_return\n"		\
"1:	ldrexd	%0, %H0, [%3]\n"					\
"	" #op1 " %Q0, %Q0, %Q4\n"					\
"	" #op2 " %R0, %R0, %R4\n"					\
"	strexd	%1, %0, %H0, [%3]\n"					\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "r" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define ATOMIC64_FETCH_OP(op, op1, op2)					\
static inline s64							\
arch_atomic64_fetch_##op##_relaxed(s64 i, atomic64_t *v)		\
{									\
	s64 result, val;						\
	unsigned long tmp;						\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic64_fetch_" #op "\n"		\
"1:	ldrexd	%0, %H0, [%4]\n"					\
"	" #op1 " %Q1, %Q0, %Q5\n"					\
"	" #op2 " %R1, %R0, %R5\n"					\
"	strexd	%2, %1, %H1, [%4]\n"					\
"	teq	%2, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter)	\
	: "r" (&v->counter), "r" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define ATOMIC64_OPS(op, op1, op2)					\
	ATOMIC64_OP(op, op1, op2)					\
	ATOMIC64_OP_RETURN(op, op1, op2)				\
	ATOMIC64_FETCH_OP(op, op1, op2)

ATOMIC64_OPS(add, adds, adc)
ATOMIC64_OPS(sub, subs, sbc)

#define arch_atomic64_add_return_relaxed	arch_atomic64_add_return_relaxed
#define arch_atomic64_sub_return_relaxed	arch_atomic64_sub_return_relaxed
#define arch_atomic64_fetch_add_relaxed		arch_atomic64_fetch_add_relaxed
#define arch_atomic64_fetch_sub_relaxed		arch_atomic64_fetch_sub_relaxed

#undef ATOMIC64_OPS
#define ATOMIC64_OPS(op, op1, op2)					\
	ATOMIC64_OP(op, op1, op2)					\
	ATOMIC64_FETCH_OP(op, op1, op2)

#define arch_atomic64_andnot arch_atomic64_andnot

ATOMIC64_OPS(and, and, and)
ATOMIC64_OPS(andnot, bic, bic)
ATOMIC64_OPS(or,  orr, orr)
ATOMIC64_OPS(xor, eor, eor)

#define arch_atomic64_fetch_and_relaxed		arch_atomic64_fetch_and_relaxed
#define arch_atomic64_fetch_andnot_relaxed	arch_atomic64_fetch_andnot_relaxed
#define arch_atomic64_fetch_or_relaxed		arch_atomic64_fetch_or_relaxed
#define arch_atomic64_fetch_xor_relaxed		arch_atomic64_fetch_xor_relaxed

#undef ATOMIC64_OPS
#undef ATOMIC64_FETCH_OP
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP

static inline s64 arch_atomic64_cmpxchg_relaxed(atomic64_t *ptr, s64 old, s64 new)
{
	s64 oldval;
	unsigned long res;

prefetchw(&ptr->counter);

do {
		__asm__ __volatile__("@ atomic64_cmpxchg\n"
		"ldrexd		%1, %H1, [%3]\n"
		"mov		%0, #0\n"
		"teq		%1, %4\n"
		"teqeq		%H1, %H4\n"
		"strexdeq	%0, %5, %H5, [%3]"
		: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
		: "r" (&ptr->counter), "r" (old), "r" (new)
		: "cc");
	} while (res);

return oldval;
}
#define arch_atomic64_cmpxchg_relaxed	arch_atomic64_cmpxchg_relaxed

static inline s64 arch_atomic64_xchg_relaxed(atomic64_t *ptr, s64 new)
{
	s64 result;
	unsigned long tmp;

prefetchw(&ptr->counter);

__asm__ __volatile__("@ atomic64_xchg\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	strexd	%1, %4, %H4, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
	: "r" (&ptr->counter), "r" (new)
	: "cc");

return result;
}
#define arch_atomic64_xchg_relaxed		arch_atomic64_xchg_relaxed

static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
{
	s64 result;
	unsigned long tmp;

smp_mb();
	prefetchw(&v->counter);

__asm__ __volatile__("@ atomic64_dec_if_positive\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	subs	%Q0, %Q0, #1\n"
"	sbc	%R0, %R0, #0\n"
"	teq	%R0, #0\n"
"	bmi	2f\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter)
	: "cc");

smp_mb();

return result;
}
#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive

static inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
{
	s64 oldval, newval;
	unsigned long tmp;

smp_mb();
	prefetchw(&v->counter);

__asm__ __volatile__("@ atomic64_add_unless\n"
"1:	ldrexd	%0, %H0, [%4]\n"
"	teq	%0, %5\n"
"	teqeq	%H0, %H5\n"
"	beq	2f\n"
"	adds	%Q1, %Q0, %Q6\n"
"	adc	%R1, %R0, %R6\n"
"	strexd	%2, %1, %H1, [%4]\n"
"	teq	%2, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (u), "r" (a)
	: "cc");

if (oldval != u)
		smp_mb();

return oldval;
}
#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless

#endif /* !CONFIG_GENERIC_ATOMIC64 */
#endif
#endif

cmd: