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/usr/src/linux-headers-5.15.0-190/arch/csky/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/csky/include/asm

Name	Size	Mode	Actions
vdso/	-	0755	rm
addrspace.h	231	0644	edit dl rm
asid.h	2440	0644	edit dl rm
barrier.h	2533	0644	edit dl rm
bitops.h	1363	0644	edit dl rm
bug.h	565	0644	edit dl rm
cache.h	861	0644	edit dl rm
cacheflush.h	193	0644	edit dl rm
checksum.h	944	0644	edit dl rm
clocksource.h	159	0644	edit dl rm
cmpxchg.h	1824	0644	edit dl rm
elf.h	2723	0644	edit dl rm
fixmap.h	747	0644	edit dl rm
ftrace.h	558	0644	edit dl rm
futex.h	2605	0644	edit dl rm
highmem.h	1114	0644	edit dl rm
io.h	1384	0644	edit dl rm
irqflags.h	1132	0644	edit dl rm
irq_work.h	208	0644	edit dl rm
Kbuild	199	0644	edit dl rm
kprobes.h	1158	0644	edit dl rm
memory.h	657	0644	edit dl rm
mmu.h	216	0644	edit dl rm
mmu_context.h	959	0644	edit dl rm
page.h	2757	0644	edit dl rm
pci.h	680	0644	edit dl rm
perf_event.h	359	0644	edit dl rm
pgalloc.h	1657	0644	edit dl rm
pgtable.h	6985	0644	edit dl rm
probes.h	554	0644	edit dl rm
processor.h	2525	0644	edit dl rm
ptrace.h	2476	0644	edit dl rm
reg_ops.h	382	0644	edit dl rm
seccomp.h	283	0644	edit dl rm
segment.h	187	0644	edit dl rm
shmparam.h	197	0644	edit dl rm
smp.h	626	0644	edit dl rm
spinlock.h	1892	0644	edit dl rm
spinlock_types.h	504	0644	edit dl rm
stackprotector.h	705	0644	edit dl rm
string.h	233	0644	edit dl rm
switch_to.h	923	0644	edit dl rm
syscall.h	1563	0644	edit dl rm
syscalls.h	351	0644	edit dl rm
tcm.h	665	0644	edit dl rm
thread_info.h	2866	0644	edit dl rm
tlb.h	508	0644	edit dl rm
tlbflush.h	824	0644	edit dl rm
traps.h	796	0644	edit dl rm
uaccess.h	5271	0644	edit dl rm
unistd.h	106	0644	edit dl rm
uprobes.h	669	0644	edit dl rm
vdso.h	784	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/csky/include/asm/barrier.h (2533B)

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_CSKY_BARRIER_H
#define __ASM_CSKY_BARRIER_H

#ifndef __ASSEMBLY__

#define nop()	asm volatile ("nop\n":::"memory")

#ifdef CONFIG_SMP

/*
 * bar.brwarws: ordering barrier for all load/store instructions
 *              before/after
 *
 * |31|30 26|25 21|20 16|15  10|9   5|4           0|
 *  1  10000 00000 00000 100001	00001 0 bw br aw ar
 *
 * b: before
 * a: after
 * r: read
 * w: write
 *
 * Here are all combinations:
 *
 * bar.brw
 * bar.br
 * bar.bw
 * bar.arw
 * bar.ar
 * bar.aw
 * bar.brwarw
 * bar.brarw
 * bar.bwarw
 * bar.brwar
 * bar.brwaw
 * bar.brar
 * bar.bwaw
 */
#define __bar_brw()	asm volatile (".long 0x842cc000\n":::"memory")
#define __bar_br()	asm volatile (".long 0x8424c000\n":::"memory")
#define __bar_bw()	asm volatile (".long 0x8428c000\n":::"memory")
#define __bar_arw()	asm volatile (".long 0x8423c000\n":::"memory")
#define __bar_ar()	asm volatile (".long 0x8421c000\n":::"memory")
#define __bar_aw()	asm volatile (".long 0x8422c000\n":::"memory")
#define __bar_brwarw()	asm volatile (".long 0x842fc000\n":::"memory")
#define __bar_brarw()	asm volatile (".long 0x8427c000\n":::"memory")
#define __bar_bwarw()	asm volatile (".long 0x842bc000\n":::"memory")
#define __bar_brwar()	asm volatile (".long 0x842dc000\n":::"memory")
#define __bar_brwaw()	asm volatile (".long 0x842ec000\n":::"memory")
#define __bar_brar()	asm volatile (".long 0x8425c000\n":::"memory")
#define __bar_brar()	asm volatile (".long 0x8425c000\n":::"memory")
#define __bar_bwaw()	asm volatile (".long 0x842ac000\n":::"memory")

#define __smp_mb()	__bar_brwarw()
#define __smp_rmb()	__bar_brar()
#define __smp_wmb()	__bar_bwaw()

#define ACQUIRE_FENCE		".long 0x8427c000\n"
#define __smp_acquire_fence()	__bar_brarw()
#define __smp_release_fence()	__bar_brwaw()

#endif /* CONFIG_SMP */

/*
 * sync:        completion barrier, all sync.xx instructions
 *              guarantee the last response received by bus transaction
 *              made by ld/st instructions before sync.s
 * sync.s:      inherit from sync, but also shareable to other cores
 * sync.i:      inherit from sync, but also flush cpu pipeline
 * sync.is:     the same with sync.i + sync.s
 */
#define mb()		asm volatile ("sync\n":::"memory")

#ifdef CONFIG_CPU_HAS_CACHEV2
/*
 * Using three sync.is to prevent speculative PTW
 */
#define sync_is()	asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory")
#endif

#include <asm-generic/barrier.h>

#endif /* __ASSEMBLY__ */
#endif /* __ASM_CSKY_BARRIER_H */

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