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/usr/src/linux-headers-5.15.0-190/arch/ia64/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/ia64/include/asm

Name	Size	Mode	Actions
native/	-	0755	rm
sn/	-	0755	rm
uv/	-	0755	rm
acenv.h	1153	0644	edit dl rm
acpi-ext.h	444	0644	edit dl rm
acpi.h	2772	0644	edit dl rm
agp.h	863	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	892	0644	edit dl rm
asmmacro.h	3372	0644	edit dl rm
atomic.h	6390	0644	edit dl rm
barrier.h	2414	0644	edit dl rm
bitops.h	11112	0644	edit dl rm
bug.h	404	0644	edit dl rm
cache.h	752	0644	edit dl rm
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cpu.h	456	0644	edit dl rm
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current.h	418	0644	edit dl rm
cyclone.h	442	0644	edit dl rm
delay.h	1738	0644	edit dl rm
device.h	236	0644	edit dl rm
div64.h	31	0644	edit dl rm
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dma.h	351	0644	edit dl rm
dmi.h	343	0644	edit dl rm
early_ioremap.h	428	0644	edit dl rm
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elf.h	10025	0644	edit dl rm
emergency-restart.h	149	0644	edit dl rm
esi.h	887	0644	edit dl rm
exception.h	609	0644	edit dl rm
export.h	115	0644	edit dl rm
extable.h	330	0644	edit dl rm
fb.h	569	0644	edit dl rm
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futex.h	2616	0644	edit dl rm
gcc_intrin.h	368	0644	edit dl rm
hardirq.h	561	0644	edit dl rm
hugetlb.h	933	0644	edit dl rm
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idle.h	200	0644	edit dl rm
intrinsics.h	306	0644	edit dl rm
io.h	7527	0644	edit dl rm
iommu.h	505	0644	edit dl rm
iommu_table.h	175	0644	edit dl rm
iosapic.h	2752	0644	edit dl rm
irq.h	960	0644	edit dl rm
irqflags.h	2096	0644	edit dl rm
irq_regs.h	34	0644	edit dl rm
irq_remapping.h	142	0644	edit dl rm
Kbuild	139	0644	edit dl rm
kdebug.h	1011	0644	edit dl rm
kexec.h	1606	0644	edit dl rm
kprobes.h	3148	0644	edit dl rm
kregs.h	6890	0644	edit dl rm
libata-portmap.h	225	0644	edit dl rm
linkage.h	398	0644	edit dl rm
local.h	31	0644	edit dl rm
mca.h	6009	0644	edit dl rm
mca_asm.h	7356	0644	edit dl rm
meminit.h	1751	0644	edit dl rm
mman.h	432	0644	edit dl rm
mmiowb.h	433	0644	edit dl rm
mmu.h	374	0644	edit dl rm
mmu_context.h	5304	0644	edit dl rm
mmzone.h	869	0644	edit dl rm
module.h	1154	0644	edit dl rm
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msidef.h	1438	0644	edit dl rm
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param.h	439	0644	edit dl rm
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patch.h	1214	0644	edit dl rm
pci.h	2007	0644	edit dl rm
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pgalloc.h	1569	0644	edit dl rm
pgtable.h	19846	0644	edit dl rm
processor.h	17876	0644	edit dl rm
ptrace.h	5258	0644	edit dl rm
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sections.h	1679	0644	edit dl rm
serial.h	446	0644	edit dl rm
shmparam.h	445	0644	edit dl rm
signal.h	749	0644	edit dl rm
smp.h	2514	0644	edit dl rm
sparsemem.h	785	0644	edit dl rm
spinlock.h	7149	0644	edit dl rm
spinlock_types.h	475	0644	edit dl rm
string.h	659	0644	edit dl rm
switch_to.h	2702	0644	edit dl rm
syscall.h	1820	0644	edit dl rm
termios.h	1923	0644	edit dl rm
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timex.h	1502	0644	edit dl rm
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topology.h	1408	0644	edit dl rm
types.h	828	0644	edit dl rm
uaccess.h	9730	0644	edit dl rm
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user.h	2299	0644	edit dl rm
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vermagic.h	341	0644	edit dl rm
vga.h	649	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
xor.h	743	0644	edit dl rm
xtp.h	938	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/ia64/include/asm/spinlock.h (7149B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_IA64_SPINLOCK_H
#define _ASM_IA64_SPINLOCK_H

/*
 * Copyright (C) 1998-2003 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
 *
 * This file is used for SMP configurations only.
 */

#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/bitops.h>

#include <linux/atomic.h>
#include <asm/intrinsics.h>
#include <asm/barrier.h>
#include <asm/processor.h>

#define arch_spin_lock_init(x)			((x)->lock = 0)

/*
 * Ticket locks are conceptually two parts, one indicating the current head of
 * the queue, and the other indicating the current tail. The lock is acquired
 * by atomically noting the tail and incrementing it by one (thus adding
 * ourself to the queue and noting our position), then waiting until the head
 * becomes equal to the initial value of the tail.
 * The pad bits in the middle are used to prevent the next_ticket number
 * overflowing into the now_serving number.
 *
 *   31             17  16    15  14                    0
 *  +----------------------------------------------------+
 *  |  now_serving     | padding |   next_ticket         |
 *  +----------------------------------------------------+
 */

#define TICKET_SHIFT	17
#define TICKET_BITS	15
#define	TICKET_MASK	((1 << TICKET_BITS) - 1)

static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
{
	int	*p = (int *)&lock->lock, ticket, serve;

ticket = ia64_fetchadd(1, p, acq);

if (!(((ticket >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
		return;

ia64_invala();

for (;;) {
		asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(p) : "memory");

if (!(((serve >> TICKET_SHIFT) ^ ticket) & TICKET_MASK))
			return;
		cpu_relax();
	}
}

static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
{
	int tmp = READ_ONCE(lock->lock);

if (!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK))
		return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp;
	return 0;
}

static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
{
	unsigned short	*p = (unsigned short *)&lock->lock + 1, tmp;

/* This could be optimised with ARCH_HAS_MMIOWB */
	mmiowb();
	asm volatile ("ld2.bias %0=[%1]" : "=r"(tmp) : "r"(p));
	WRITE_ONCE(*p, (tmp + 2) & ~1);
}

static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
{
	long tmp = READ_ONCE(lock->lock);

return !!(((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK);
}

static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
{
	long tmp = READ_ONCE(lock->lock);

return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
}

static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
	return !(((lock.lock >> TICKET_SHIFT) ^ lock.lock) & TICKET_MASK);
}

static inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
	return __ticket_spin_is_locked(lock);
}

static inline int arch_spin_is_contended(arch_spinlock_t *lock)
{
	return __ticket_spin_is_contended(lock);
}
#define arch_spin_is_contended	arch_spin_is_contended

static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
{
	__ticket_spin_lock(lock);
}

static __always_inline int arch_spin_trylock(arch_spinlock_t *lock)
{
	return __ticket_spin_trylock(lock);
}

static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
{
	__ticket_spin_unlock(lock);
}

static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock,
						  unsigned long flags)
{
	arch_spin_lock(lock);
}
#define arch_spin_lock_flags	arch_spin_lock_flags

#ifdef ASM_SUPPORTED

static __always_inline void
arch_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
{
	__asm__ __volatile__ (
		"tbit.nz p6, p0 = %1,%2\n"
		"br.few 3f\n"
		"1:\n"
		"fetchadd4.rel r2 = [%0], -1;;\n"
		"(p6) ssm psr.i\n"
		"2:\n"
		"hint @pause\n"
		"ld4 r2 = [%0];;\n"
		"cmp4.lt p7,p0 = r2, r0\n"
		"(p7) br.cond.spnt.few 2b\n"
		"(p6) rsm psr.i\n"
		";;\n"
		"3:\n"
		"fetchadd4.acq r2 = [%0], 1;;\n"
		"cmp4.lt p7,p0 = r2, r0\n"
		"(p7) br.cond.spnt.few 1b\n"
		: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
		: "p6", "p7", "r2", "memory");
}

#define arch_read_lock_flags arch_read_lock_flags
#define arch_read_lock(lock) arch_read_lock_flags(lock, 0)

#else /* !ASM_SUPPORTED */

#define arch_read_lock_flags(rw, flags) arch_read_lock(rw)

#define arch_read_lock(rw)								\
do {											\
	arch_rwlock_t *__read_lock_ptr = (rw);						\
											\
	while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {		\
		ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);			\
		while (*(volatile int *)__read_lock_ptr < 0)				\
			cpu_relax();							\
	}										\
} while (0)

#endif /* !ASM_SUPPORTED */

#define arch_read_unlock(rw)					\
do {								\
	arch_rwlock_t *__read_lock_ptr = (rw);			\
	ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);	\
} while (0)

#ifdef ASM_SUPPORTED

static __always_inline void
arch_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
{
	__asm__ __volatile__ (
		"tbit.nz p6, p0 = %1, %2\n"
		"mov ar.ccv = r0\n"
		"dep r29 = -1, r0, 31, 1\n"
		"br.few 3f;;\n"
		"1:\n"
		"(p6) ssm psr.i\n"
		"2:\n"
		"hint @pause\n"
		"ld4 r2 = [%0];;\n"
		"cmp4.eq p0,p7 = r0, r2\n"
		"(p7) br.cond.spnt.few 2b\n"
		"(p6) rsm psr.i\n"
		";;\n"
		"3:\n"
		"cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
		"cmp4.eq p0,p7 = r0, r2\n"
		"(p7) br.cond.spnt.few 1b;;\n"
		: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
		: "ar.ccv", "p6", "p7", "r2", "r29", "memory");
}

#define arch_write_lock_flags arch_write_lock_flags
#define arch_write_lock(rw) arch_write_lock_flags(rw, 0)

#define arch_write_trylock(rw)							\
({										\
	register long result;							\
										\
	__asm__ __volatile__ (							\
		"mov ar.ccv = r0\n"						\
		"dep r29 = -1, r0, 31, 1;;\n"					\
		"cmpxchg4.acq %0 = [%1], r29, ar.ccv\n"				\
		: "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory");		\
	(result == 0);								\
})

static inline void arch_write_unlock(arch_rwlock_t *x)
{
	u8 *y = (u8 *)x;
	barrier();
	asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
}

#else /* !ASM_SUPPORTED */

#define arch_write_lock(l)								\
({											\
	__u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1);			\
	__u32 *ia64_write_lock_ptr = (__u32 *) (l);					\
	do {										\
		while (*ia64_write_lock_ptr)						\
			ia64_barrier();							\
		ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0);	\
	} while (ia64_val);								\
})

#define arch_write_trylock(rw)						\
({									\
	__u64 ia64_val;							\
	__u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1);			\
	ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0);	\
	(ia64_val == 0);						\
})

static inline void arch_write_unlock(arch_rwlock_t *x)
{
	barrier();
	x->write_lock = 0;
}

#endif /* !ASM_SUPPORTED */

static inline int arch_read_trylock(arch_rwlock_t *x)
{
	union {
		arch_rwlock_t lock;
		__u32 word;
	} old, new;
	old.lock = new.lock = *x;
	old.lock.write_lock = new.lock.write_lock = 0;
	++new.lock.read_counter;
	return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
}

#endif /*  _ASM_IA64_SPINLOCK_H */

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