FM / asm

/usr/src/linux-headers-5.15.0-190/arch/m68k/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/m68k/include/asm

Name	Size	Mode	Actions
adb_iop.h	1188	0644	edit dl rm
amigahw.h	10737	0644	edit dl rm
amigaints.h	3583	0644	edit dl rm
amigayle.h	3271	0644	edit dl rm
amipcmcia.h	2568	0644	edit dl rm
apollohw.h	2410	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	211	0644	edit dl rm
atarihw.h	20919	0644	edit dl rm
atariints.h	5691	0644	edit dl rm
atarikb.h	1434	0644	edit dl rm
atari_joystick.h	457	0644	edit dl rm
atari_stdma.h	514	0644	edit dl rm
atari_stram.h	528	0644	edit dl rm
atomic.h	5016	0644	edit dl rm
bitops.h	12827	0644	edit dl rm
blinken.h	641	0644	edit dl rm
bootinfo.h	783	0644	edit dl rm
bootstd.h	4747	0644	edit dl rm
bug.h	659	0644	edit dl rm
bvme6000hw.h	3529	0644	edit dl rm
cache.h	296	0644	edit dl rm
cacheflush.h	133	0644	edit dl rm
cacheflush_mm.h	7173	0644	edit dl rm
cacheflush_no.h	1884	0644	edit dl rm
checksum.h	3497	0644	edit dl rm
cmpxchg.h	3189	0644	edit dl rm
coldfire.h	1653	0644	edit dl rm
contregs.h	3390	0644	edit dl rm
current.h	580	0644	edit dl rm
delay.h	3504	0644	edit dl rm
div64.h	858	0644	edit dl rm
dma.h	17040	0644	edit dl rm
dsp56k.h	1269	0644	edit dl rm
dvma.h	9903	0644	edit dl rm
elf.h	3145	0644	edit dl rm
entry.h	5902	0644	edit dl rm
export.h	53	0644	edit dl rm
fb.h	921	0644	edit dl rm
fbio.h	10106	0644	edit dl rm
flat.h	333	0644	edit dl rm
floppy.h	5330	0644	edit dl rm
fpu.h	535	0644	edit dl rm
ftrace.h	12	0644	edit dl rm
gpio.h	2294	0644	edit dl rm
hash.h	2115	0644	edit dl rm
hp300hw.h	186	0644	edit dl rm
hwtest.h	467	0644	edit dl rm
ide.h	1708	0644	edit dl rm
idprom.h	725	0644	edit dl rm
intersil.h	1134	0644	edit dl rm
io.h	244	0644	edit dl rm
io_mm.h	13198	0644	edit dl rm
io_no.h	4196	0644	edit dl rm
irq.h	2634	0644	edit dl rm
irqflags.h	1652	0644	edit dl rm
Kbuild	165	0644	edit dl rm
kexec.h	732	0644	edit dl rm
kmap.h	1754	0644	edit dl rm
linkage.h	1583	0644	edit dl rm
m52xxacr.h	3660	0644	edit dl rm
m53xxacr.h	3683	0644	edit dl rm
m53xxsim.h	55262	0644	edit dl rm
m54xxacr.h	4934	0644	edit dl rm
m54xxgpt.h	3750	0644	edit dl rm
m54xxpci.h	6276	0644	edit dl rm
m54xxsim.h	3892	0644	edit dl rm
m520xsim.h	7323	0644	edit dl rm
m523xsim.h	7882	0644	edit dl rm
m525xsim.h	10822	0644	edit dl rm
m527xsim.h	13835	0644	edit dl rm
m528xsim.h	9599	0644	edit dl rm
m5206sim.h	6555	0644	edit dl rm
m5272sim.h	6199	0644	edit dl rm
m5307sim.h	7698	0644	edit dl rm
m5407sim.h	6289	0644	edit dl rm
m5441xsim.h	10294	0644	edit dl rm
machdep.h	1331	0644	edit dl rm
machines.h	3209	0644	edit dl rm
machw.h	588	0644	edit dl rm
macintosh.h	2438	0644	edit dl rm
macints.h	3210	0644	edit dl rm
mac_asc.h	520	0644	edit dl rm
mac_baboon.h	999	0644	edit dl rm
mac_iop.h	5499	0644	edit dl rm
mac_oss.h	1873	0644	edit dl rm
mac_psc.h	7427	0644	edit dl rm
mac_via.h	11718	0644	edit dl rm
math-emu.h	6897	0644	edit dl rm
MC68EZ328.h	38650	0644	edit dl rm
MC68VZ328.h	42006	0644	edit dl rm
MC68328.h	38724	0644	edit dl rm
mc146818rtc.h	598	0644	edit dl rm
mcf8390.h	3844	0644	edit dl rm
mcfclk.h	961	0644	edit dl rm
mcfdma.h	6662	0644	edit dl rm
mcfgpio.h	8269	0644	edit dl rm
mcfintc.h	3161	0644	edit dl rm
mcfmmu.h	3761	0644	edit dl rm
mcfpit.h	2278	0644	edit dl rm
mcfqspi.h	1466	0644	edit dl rm
mcfsim.h	1531	0644	edit dl rm
mcfslt.h	1240	0644	edit dl rm
mcftimer.h	2357	0644	edit dl rm
mcfuart.h	7076	0644	edit dl rm
mcfwdebug.h	5106	0644	edit dl rm
mcf_pgalloc.h	2000	0644	edit dl rm
mcf_pgtable.h	8312	0644	edit dl rm
mmu.h	243	0644	edit dl rm
mmu_context.h	7207	0644	edit dl rm
module.h	847	0644	edit dl rm
module.lds.h	91	0644	edit dl rm
motorola_pgalloc.h	2146	0644	edit dl rm
motorola_pgtable.h	7610	0644	edit dl rm
movs.h	1472	0644	edit dl rm
mvme16xhw.h	2216	0644	edit dl rm
mvme147hw.h	2938	0644	edit dl rm
natfeat.h	533	0644	edit dl rm
nettel.h	3023	0644	edit dl rm
nubus.h	1262	0644	edit dl rm
openprom.h	8173	0644	edit dl rm
oplib.h	9768	0644	edit dl rm
page.h	1728	0644	edit dl rm
page_mm.h	3399	0644	edit dl rm
page_no.h	1322	0644	edit dl rm
page_offset.h	256	0644	edit dl rm
parport.h	837	0644	edit dl rm
pci.h	258	0644	edit dl rm
pgalloc.h	444	0644	edit dl rm
pgtable.h	127	0644	edit dl rm
pgtable_mm.h	4931	0644	edit dl rm
pgtable_no.h	1438	0644	edit dl rm
processor.h	4158	0644	edit dl rm
ptrace.h	643	0644	edit dl rm
q40ints.h	749	0644	edit dl rm
q40_master.h	2357	0644	edit dl rm
quicc_simple.h	1830	0644	edit dl rm
raw_io.h	12003	0644	edit dl rm
serial.h	1165	0644	edit dl rm
setup.h	9467	0644	edit dl rm
signal.h	1377	0644	edit dl rm
smp.h	32	0644	edit dl rm
string.h	1717	0644	edit dl rm
sun3-head.h	353	0644	edit dl rm
sun3ints.h	989	0644	edit dl rm
sun3mmu.h	5025	0644	edit dl rm
sun3x.h	868	0644	edit dl rm
sun3xflop.h	5757	0644	edit dl rm
sun3xprom.h	1343	0644	edit dl rm
sun3_pgalloc.h	1267	0644	edit dl rm
sun3_pgtable.h	6583	0644	edit dl rm
switch_to.h	1549	0644	edit dl rm
syscall.h	251	0644	edit dl rm
thread_info.h	2237	0644	edit dl rm
timex.h	974	0644	edit dl rm
tlb.h	135	0644	edit dl rm
tlbflush.h	5989	0644	edit dl rm
traps.h	8615	0644	edit dl rm
uaccess.h	12563	0644	edit dl rm
ucontext.h	570	0644	edit dl rm
unistd.h	993	0644	edit dl rm
user.h	3874	0644	edit dl rm
vga.h	902	0644	edit dl rm
virtconvert.h	834	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
zorro.h	1222	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/m68k/include/asm/bitops.h (12827B)

#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
/*
 * Copyright 1992, Linus Torvalds.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/compiler.h>
#include <asm/barrier.h>

/*
 *	Bit access functions vary across the ColdFire and 68k families.
 *	So we will break them out here, and then macro in the ones we want.
 *
 *	ColdFire - supports standard bset/bclr/bchg with register operand only
 *	68000    - supports standard bset/bclr/bchg with memory operand
 *	>= 68020 - also supports the bfset/bfclr/bfchg instructions
 *
 *	Although it is possible to use only the bset/bclr/bchg with register
 *	operands on all platforms you end up with larger generated code.
 *	So we use the best form possible on a given platform.
 */

static inline void bset_reg_set_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bset %1,(%0)"
		:
		: "a" (p), "di" (nr & 7)
		: "memory");
}

static inline void bset_mem_set_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bset %1,%0"
		: "+m" (*p)
		: "di" (nr & 7));
}

static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr)
{
	__asm__ __volatile__ ("bfset %1{%0:#1}"
		:
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
}

#if defined(CONFIG_COLDFIRE)
#define	set_bit(nr, vaddr)	bset_reg_set_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	set_bit(nr, vaddr)	bset_mem_set_bit(nr, vaddr)
#else
#define set_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
				bset_mem_set_bit(nr, vaddr) : \
				bfset_mem_set_bit(nr, vaddr))
#endif

#define __set_bit(nr, vaddr)	set_bit(nr, vaddr)

static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bclr %1,(%0)"
		:
		: "a" (p), "di" (nr & 7)
		: "memory");
}

static inline void bclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bclr %1,%0"
		: "+m" (*p)
		: "di" (nr & 7));
}

static inline void bfclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
{
	__asm__ __volatile__ ("bfclr %1{%0:#1}"
		:
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
}

#if defined(CONFIG_COLDFIRE)
#define	clear_bit(nr, vaddr)	bclr_reg_clear_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	clear_bit(nr, vaddr)	bclr_mem_clear_bit(nr, vaddr)
#else
#define clear_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
				bclr_mem_clear_bit(nr, vaddr) : \
				bfclr_mem_clear_bit(nr, vaddr))
#endif

#define __clear_bit(nr, vaddr)	clear_bit(nr, vaddr)

static inline void bchg_reg_change_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bchg %1,(%0)"
		:
		: "a" (p), "di" (nr & 7)
		: "memory");
}

static inline void bchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;

__asm__ __volatile__ ("bchg %1,%0"
		: "+m" (*p)
		: "di" (nr & 7));
}

static inline void bfchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
{
	__asm__ __volatile__ ("bfchg %1{%0:#1}"
		:
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
}

#if defined(CONFIG_COLDFIRE)
#define	change_bit(nr, vaddr)	bchg_reg_change_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	change_bit(nr, vaddr)	bchg_mem_change_bit(nr, vaddr)
#else
#define change_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
				bchg_mem_change_bit(nr, vaddr) : \
				bfchg_mem_change_bit(nr, vaddr))
#endif

#define __change_bit(nr, vaddr)	change_bit(nr, vaddr)

static inline int test_bit(int nr, const volatile unsigned long *vaddr)
{
	return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
}

static inline int bset_reg_test_and_set_bit(int nr,
					    volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bset %2,(%1); sne %0"
		: "=d" (retval)
		: "a" (p), "di" (nr & 7)
		: "memory");
	return retval;
}

static inline int bset_mem_test_and_set_bit(int nr,
					    volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bset %2,%1; sne %0"
		: "=d" (retval), "+m" (*p)
		: "di" (nr & 7));
	return retval;
}

static inline int bfset_mem_test_and_set_bit(int nr,
					     volatile unsigned long *vaddr)
{
	char retval;

__asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
		: "=d" (retval)
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
	return retval;
}

#if defined(CONFIG_COLDFIRE)
#define	test_and_set_bit(nr, vaddr)	bset_reg_test_and_set_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	test_and_set_bit(nr, vaddr)	bset_mem_test_and_set_bit(nr, vaddr)
#else
#define test_and_set_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
					bset_mem_test_and_set_bit(nr, vaddr) : \
					bfset_mem_test_and_set_bit(nr, vaddr))
#endif

#define __test_and_set_bit(nr, vaddr)	test_and_set_bit(nr, vaddr)

static inline int bclr_reg_test_and_clear_bit(int nr,
					      volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bclr %2,(%1); sne %0"
		: "=d" (retval)
		: "a" (p), "di" (nr & 7)
		: "memory");
	return retval;
}

static inline int bclr_mem_test_and_clear_bit(int nr,
					      volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bclr %2,%1; sne %0"
		: "=d" (retval), "+m" (*p)
		: "di" (nr & 7));
	return retval;
}

static inline int bfclr_mem_test_and_clear_bit(int nr,
					       volatile unsigned long *vaddr)
{
	char retval;

__asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
		: "=d" (retval)
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
	return retval;
}

#if defined(CONFIG_COLDFIRE)
#define	test_and_clear_bit(nr, vaddr)	bclr_reg_test_and_clear_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	test_and_clear_bit(nr, vaddr)	bclr_mem_test_and_clear_bit(nr, vaddr)
#else
#define test_and_clear_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
					bclr_mem_test_and_clear_bit(nr, vaddr) : \
					bfclr_mem_test_and_clear_bit(nr, vaddr))
#endif

#define __test_and_clear_bit(nr, vaddr)	test_and_clear_bit(nr, vaddr)

static inline int bchg_reg_test_and_change_bit(int nr,
					       volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bchg %2,(%1); sne %0"
		: "=d" (retval)
		: "a" (p), "di" (nr & 7)
		: "memory");
	return retval;
}

static inline int bchg_mem_test_and_change_bit(int nr,
					       volatile unsigned long *vaddr)
{
	char *p = (char *)vaddr + (nr ^ 31) / 8;
	char retval;

__asm__ __volatile__ ("bchg %2,%1; sne %0"
		: "=d" (retval), "+m" (*p)
		: "di" (nr & 7));
	return retval;
}

static inline int bfchg_mem_test_and_change_bit(int nr,
						volatile unsigned long *vaddr)
{
	char retval;

__asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
		: "=d" (retval)
		: "d" (nr ^ 31), "o" (*vaddr)
		: "memory");
	return retval;
}

#if defined(CONFIG_COLDFIRE)
#define	test_and_change_bit(nr, vaddr)	bchg_reg_test_and_change_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define	test_and_change_bit(nr, vaddr)	bchg_mem_test_and_change_bit(nr, vaddr)
#else
#define test_and_change_bit(nr, vaddr)	(__builtin_constant_p(nr) ? \
					bchg_mem_test_and_change_bit(nr, vaddr) : \
					bfchg_mem_test_and_change_bit(nr, vaddr))
#endif

#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)

/*
 *	The true 68020 and more advanced processors support the "bfffo"
 *	instruction for finding bits. ColdFire and simple 68000 parts
 *	(including CPU32) do not support this. They simply use the generic
 *	functions.
 */
#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#include <asm-generic/bitops/ffz.h>
#else

static inline unsigned long find_first_zero_bit(const unsigned long *vaddr,
						unsigned long size)
{
	const unsigned long *p = vaddr;
	unsigned long res = 32;
	unsigned long words;
	unsigned long num;

if (!size)
		return 0;

words = (size + 31) >> 5;
	while (!(num = ~*p++)) {
		if (!--words)
			goto out;
	}

__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
			      : "=d" (res) : "d" (num & -num));
	res ^= 31;
out:
	res += ((long)p - (long)vaddr - 4) * 8;
	return res < size ? res : size;
}
#define find_first_zero_bit find_first_zero_bit

static inline unsigned long find_next_zero_bit(const unsigned long *vaddr,
					       unsigned long size,
					       unsigned long offset)
{
	const unsigned long *p = vaddr + (offset >> 5);
	int bit = offset & 31UL, res;

if (offset >= size)
		return size;

if (bit) {
		unsigned long num = ~*p++ & (~0UL << bit);
		offset -= bit;

/* Look for zero in first longword */
		__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
				      : "=d" (res) : "d" (num & -num));
		if (res < 32) {
			offset += res ^ 31;
			return offset < size ? offset : size;
		}
		offset += 32;

if (offset >= size)
			return size;
	}
	/* No zero yet, search remaining full bytes for a zero */
	return offset + find_first_zero_bit(p, size - offset);
}
#define find_next_zero_bit find_next_zero_bit

static inline unsigned long find_first_bit(const unsigned long *vaddr,
					   unsigned long size)
{
	const unsigned long *p = vaddr;
	unsigned long res = 32;
	unsigned long words;
	unsigned long num;

if (!size)
		return 0;

words = (size + 31) >> 5;
	while (!(num = *p++)) {
		if (!--words)
			goto out;
	}

static inline unsigned long find_next_bit(const unsigned long *vaddr,
					  unsigned long size,
					  unsigned long offset)
{
	const unsigned long *p = vaddr + (offset >> 5);
	int bit = offset & 31UL, res;

if (offset >= size)
		return size;

if (bit) {
		unsigned long num = *p++ & (~0UL << bit);
		offset -= bit;

/* Look for one in first longword */
		__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
				      : "=d" (res) : "d" (num & -num));
		if (res < 32) {
			offset += res ^ 31;
			return offset < size ? offset : size;
		}
		offset += 32;

if (offset >= size)
			return size;
	}
	/* No one yet, search remaining full bytes for a one */
	return offset + find_first_bit(p, size - offset);
}
#define find_next_bit find_next_bit

/*
 * ffz = Find First Zero in word. Undefined if no zero exists,
 * so code should check against ~0UL first..
 */
static inline unsigned long ffz(unsigned long word)
{
	int res;

__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
			      : "=d" (res) : "d" (~word & -~word));
	return res ^ 31;
}

#endif

#ifdef __KERNEL__

#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)

/*
 *	The newer ColdFire family members support a "bitrev" instruction
 *	and we can use that to implement a fast ffs. Older Coldfire parts,
 *	and normal 68000 parts don't have anything special, so we use the
 *	generic functions for those.
 */
#if (defined(__mcfisaaplus__) || defined(__mcfisac__)) && \
	!defined(CONFIG_M68000) && !defined(CONFIG_MCPU32)
static inline unsigned long __ffs(unsigned long x)
{
	__asm__ __volatile__ ("bitrev %0; ff1 %0"
		: "=d" (x)
		: "0" (x));
	return x;
}

static inline int ffs(int x)
{
	if (!x)
		return 0;
	return __ffs(x) + 1;
}

#else
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/__ffs.h>
#endif

#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>

#else

/*
 *	ffs: find first bit set. This is defined the same way as
 *	the libc and compiler builtin ffs routines, therefore
 *	differs in spirit from the above ffz (man ffs).
 */
static inline int ffs(int x)
{
	int cnt;

__asm__ ("bfffo %1{#0:#0},%0"
		: "=d" (cnt)
		: "dm" (x & -x));
	return 32 - cnt;
}

static inline unsigned long __ffs(unsigned long x)
{
	return ffs(x) - 1;
}

/*
 *	fls: find last bit set.
 */
static inline int fls(unsigned int x)
{
	int cnt;

__asm__ ("bfffo %1{#0,#0},%0"
		: "=d" (cnt)
		: "dm" (x));
	return 32 - cnt;
}

static inline int __fls(int x)
{
	return fls(x) - 1;
}

#endif

/* Simple test-and-set bit locks */
#define test_and_set_bit_lock	test_and_set_bit
#define clear_bit_unlock	clear_bit
#define __clear_bit_unlock	clear_bit_unlock

#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/le.h>
#endif /* __KERNEL__ */

#include <asm-generic/bitops/find.h>

#endif /* _M68K_BITOPS_H */

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