FM / asm

/usr/src/linux-headers-5.15.0-190/arch/m68k/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/m68k/include/asm

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adb_iop.h	1188	0644	edit dl rm
amigahw.h	10737	0644	edit dl rm
amigaints.h	3583	0644	edit dl rm
amigayle.h	3271	0644	edit dl rm
amipcmcia.h	2568	0644	edit dl rm
apollohw.h	2410	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	211	0644	edit dl rm
atarihw.h	20919	0644	edit dl rm
atariints.h	5691	0644	edit dl rm
atarikb.h	1434	0644	edit dl rm
atari_joystick.h	457	0644	edit dl rm
atari_stdma.h	514	0644	edit dl rm
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atomic.h	5016	0644	edit dl rm
bitops.h	12827	0644	edit dl rm
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bootinfo.h	783	0644	edit dl rm
bootstd.h	4747	0644	edit dl rm
bug.h	659	0644	edit dl rm
bvme6000hw.h	3529	0644	edit dl rm
cache.h	296	0644	edit dl rm
cacheflush.h	133	0644	edit dl rm
cacheflush_mm.h	7173	0644	edit dl rm
cacheflush_no.h	1884	0644	edit dl rm
checksum.h	3497	0644	edit dl rm
cmpxchg.h	3189	0644	edit dl rm
coldfire.h	1653	0644	edit dl rm
contregs.h	3390	0644	edit dl rm
current.h	580	0644	edit dl rm
delay.h	3504	0644	edit dl rm
div64.h	858	0644	edit dl rm
dma.h	17040	0644	edit dl rm
dsp56k.h	1269	0644	edit dl rm
dvma.h	9903	0644	edit dl rm
elf.h	3145	0644	edit dl rm
entry.h	5902	0644	edit dl rm
export.h	53	0644	edit dl rm
fb.h	921	0644	edit dl rm
fbio.h	10106	0644	edit dl rm
flat.h	333	0644	edit dl rm
floppy.h	5330	0644	edit dl rm
fpu.h	535	0644	edit dl rm
ftrace.h	12	0644	edit dl rm
gpio.h	2294	0644	edit dl rm
hash.h	2115	0644	edit dl rm
hp300hw.h	186	0644	edit dl rm
hwtest.h	467	0644	edit dl rm
ide.h	1708	0644	edit dl rm
idprom.h	725	0644	edit dl rm
intersil.h	1134	0644	edit dl rm
io.h	244	0644	edit dl rm
io_mm.h	13198	0644	edit dl rm
io_no.h	4196	0644	edit dl rm
irq.h	2634	0644	edit dl rm
irqflags.h	1652	0644	edit dl rm
Kbuild	165	0644	edit dl rm
kexec.h	732	0644	edit dl rm
kmap.h	1754	0644	edit dl rm
linkage.h	1583	0644	edit dl rm
m52xxacr.h	3660	0644	edit dl rm
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m53xxsim.h	55262	0644	edit dl rm
m54xxacr.h	4934	0644	edit dl rm
m54xxgpt.h	3750	0644	edit dl rm
m54xxpci.h	6276	0644	edit dl rm
m54xxsim.h	3892	0644	edit dl rm
m520xsim.h	7323	0644	edit dl rm
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m527xsim.h	13835	0644	edit dl rm
m528xsim.h	9599	0644	edit dl rm
m5206sim.h	6555	0644	edit dl rm
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m5307sim.h	7698	0644	edit dl rm
m5407sim.h	6289	0644	edit dl rm
m5441xsim.h	10294	0644	edit dl rm
machdep.h	1331	0644	edit dl rm
machines.h	3209	0644	edit dl rm
machw.h	588	0644	edit dl rm
macintosh.h	2438	0644	edit dl rm
macints.h	3210	0644	edit dl rm
mac_asc.h	520	0644	edit dl rm
mac_baboon.h	999	0644	edit dl rm
mac_iop.h	5499	0644	edit dl rm
mac_oss.h	1873	0644	edit dl rm
mac_psc.h	7427	0644	edit dl rm
mac_via.h	11718	0644	edit dl rm
math-emu.h	6897	0644	edit dl rm
MC68EZ328.h	38650	0644	edit dl rm
MC68VZ328.h	42006	0644	edit dl rm
MC68328.h	38724	0644	edit dl rm
mc146818rtc.h	598	0644	edit dl rm
mcf8390.h	3844	0644	edit dl rm
mcfclk.h	961	0644	edit dl rm
mcfdma.h	6662	0644	edit dl rm
mcfgpio.h	8269	0644	edit dl rm
mcfintc.h	3161	0644	edit dl rm
mcfmmu.h	3761	0644	edit dl rm
mcfpit.h	2278	0644	edit dl rm
mcfqspi.h	1466	0644	edit dl rm
mcfsim.h	1531	0644	edit dl rm
mcfslt.h	1240	0644	edit dl rm
mcftimer.h	2357	0644	edit dl rm
mcfuart.h	7076	0644	edit dl rm
mcfwdebug.h	5106	0644	edit dl rm
mcf_pgalloc.h	2000	0644	edit dl rm
mcf_pgtable.h	8312	0644	edit dl rm
mmu.h	243	0644	edit dl rm
mmu_context.h	7207	0644	edit dl rm
module.h	847	0644	edit dl rm
module.lds.h	91	0644	edit dl rm
motorola_pgalloc.h	2146	0644	edit dl rm
motorola_pgtable.h	7610	0644	edit dl rm
movs.h	1472	0644	edit dl rm
mvme16xhw.h	2216	0644	edit dl rm
mvme147hw.h	2938	0644	edit dl rm
natfeat.h	533	0644	edit dl rm
nettel.h	3023	0644	edit dl rm
nubus.h	1262	0644	edit dl rm
openprom.h	8173	0644	edit dl rm
oplib.h	9768	0644	edit dl rm
page.h	1728	0644	edit dl rm
page_mm.h	3399	0644	edit dl rm
page_no.h	1322	0644	edit dl rm
page_offset.h	256	0644	edit dl rm
parport.h	837	0644	edit dl rm
pci.h	258	0644	edit dl rm
pgalloc.h	444	0644	edit dl rm
pgtable.h	127	0644	edit dl rm
pgtable_mm.h	4931	0644	edit dl rm
pgtable_no.h	1438	0644	edit dl rm
processor.h	4158	0644	edit dl rm
ptrace.h	643	0644	edit dl rm
q40ints.h	749	0644	edit dl rm
q40_master.h	2357	0644	edit dl rm
quicc_simple.h	1830	0644	edit dl rm
raw_io.h	12003	0644	edit dl rm
serial.h	1165	0644	edit dl rm
setup.h	9467	0644	edit dl rm
signal.h	1377	0644	edit dl rm
smp.h	32	0644	edit dl rm
string.h	1717	0644	edit dl rm
sun3-head.h	353	0644	edit dl rm
sun3ints.h	989	0644	edit dl rm
sun3mmu.h	5025	0644	edit dl rm
sun3x.h	868	0644	edit dl rm
sun3xflop.h	5757	0644	edit dl rm
sun3xprom.h	1343	0644	edit dl rm
sun3_pgalloc.h	1267	0644	edit dl rm
sun3_pgtable.h	6583	0644	edit dl rm
switch_to.h	1549	0644	edit dl rm
syscall.h	251	0644	edit dl rm
thread_info.h	2237	0644	edit dl rm
timex.h	974	0644	edit dl rm
tlb.h	135	0644	edit dl rm
tlbflush.h	5989	0644	edit dl rm
traps.h	8615	0644	edit dl rm
uaccess.h	12563	0644	edit dl rm
ucontext.h	570	0644	edit dl rm
unistd.h	993	0644	edit dl rm
user.h	3874	0644	edit dl rm
vga.h	902	0644	edit dl rm
virtconvert.h	834	0644	edit dl rm
vmalloc.h	90	0644	edit dl rm
zorro.h	1222	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/m68k/include/asm/m54xxpci.h (6276B)

/****************************************************************************/

/*
 *	m54xxpci.h -- ColdFire 547x and 548x PCI bus support
 *
 *	(C) Copyright 2011,  Greg Ungerer <gerg@uclinux.org>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

/****************************************************************************/
#ifndef	M54XXPCI_H
#define	M54XXPCI_H
/****************************************************************************/

/*
 *	The core set of PCI support registers are mapped into the MBAR region.
 */
#define	PCIIDR		(CONFIG_MBAR + 0xb00)	/* PCI device/vendor ID */
#define	PCISCR		(CONFIG_MBAR + 0xb04)	/* PCI status/command */
#define	PCICCRIR	(CONFIG_MBAR + 0xb08)	/* PCI class/revision */
#define	PCICR1		(CONFIG_MBAR + 0xb0c)	/* PCI configuration 1 */
#define	PCIBAR0		(CONFIG_MBAR + 0xb10)	/* PCI base address 0 */
#define	PCIBAR1		(CONFIG_MBAR + 0xb14)	/* PCI base address 1 */
#define	PCICCPR		(CONFIG_MBAR + 0xb28)	/* PCI cardbus CIS pointer */
#define	PCISID		(CONFIG_MBAR + 0xb2c)	/* PCI subsystem IDs */
#define	PCIERBAR	(CONFIG_MBAR + 0xb30)	/* PCI expansion ROM */
#define	PCICPR		(CONFIG_MBAR + 0xb34)	/* PCI capabilities pointer */
#define	PCICR2		(CONFIG_MBAR + 0xb3c)	/* PCI configuration 2 */

#define	PCIGSCR		(CONFIG_MBAR + 0xb60)	/* Global status/control */
#define	PCITBATR0	(CONFIG_MBAR + 0xb64)	/* Target base translation 0 */
#define	PCITBATR1	(CONFIG_MBAR + 0xb68)	/* Target base translation 1 */
#define	PCITCR		(CONFIG_MBAR + 0xb6c)	/* Target control */
#define	PCIIW0BTAR	(CONFIG_MBAR + 0xb70)	/* Initiator window 0 */
#define	PCIIW1BTAR	(CONFIG_MBAR + 0xb74)	/* Initiator window 1 */
#define	PCIIW2BTAR	(CONFIG_MBAR + 0xb78)	/* Initiator window 2 */
#define	PCIIWCR		(CONFIG_MBAR + 0xb80)	/* Initiator window config */
#define	PCIICR		(CONFIG_MBAR + 0xb84)	/* Initiator control */
#define	PCIISR		(CONFIG_MBAR + 0xb88)	/* Initiator status */
#define	PCICAR		(CONFIG_MBAR + 0xbf8)	/* Configuration address */

#define	PCITPSR		(CONFIG_MBAR + 0x8400)	/* TX packet size */
#define	PCITSAR		(CONFIG_MBAR + 0x8404)	/* TX start address */
#define	PCITTCR		(CONFIG_MBAR + 0x8408)	/* TX transaction control */
#define	PCITER		(CONFIG_MBAR + 0x840c)	/* TX enables */
#define	PCITNAR		(CONFIG_MBAR + 0x8410)	/* TX next address */
#define	PCITLWR		(CONFIG_MBAR + 0x8414)	/* TX last word */
#define	PCITDCR		(CONFIG_MBAR + 0x8418)	/* TX done counts */
#define	PCITSR		(CONFIG_MBAR + 0x841c)	/* TX status */
#define	PCITFDR		(CONFIG_MBAR + 0x8440)	/* TX FIFO data */
#define	PCITFSR		(CONFIG_MBAR + 0x8444)	/* TX FIFO status */
#define	PCITFCR		(CONFIG_MBAR + 0x8448)	/* TX FIFO control */
#define	PCITFAR		(CONFIG_MBAR + 0x844c)	/* TX FIFO alarm */
#define	PCITFRPR	(CONFIG_MBAR + 0x8450)	/* TX FIFO read pointer */
#define	PCITFWPR	(CONFIG_MBAR + 0x8454)	/* TX FIFO write pointer */

#define	PCIRPSR		(CONFIG_MBAR + 0x8480)	/* RX packet size */
#define	PCIRSAR		(CONFIG_MBAR + 0x8484)	/* RX start address */
#define	PCIRTCR		(CONFIG_MBAR + 0x8488)	/* RX transaction control */
#define	PCIRER		(CONFIG_MBAR + 0x848c)	/* RX enables */
#define	PCIRNAR		(CONFIG_MBAR + 0x8490)	/* RX next address */
#define	PCIRDCR		(CONFIG_MBAR + 0x8498)	/* RX done counts */
#define	PCIRSR		(CONFIG_MBAR + 0x849c)	/* RX status */
#define	PCIRFDR		(CONFIG_MBAR + 0x84c0)	/* RX FIFO data */
#define	PCIRFSR		(CONFIG_MBAR + 0x84c4)	/* RX FIFO status */
#define	PCIRFCR		(CONFIG_MBAR + 0x84c8)	/* RX FIFO control */
#define	PCIRFAR		(CONFIG_MBAR + 0x84cc)	/* RX FIFO alarm */
#define	PCIRFRPR	(CONFIG_MBAR + 0x84d0)	/* RX FIFO read pointer */
#define	PCIRFWPR	(CONFIG_MBAR + 0x84d4)	/* RX FIFO write pointer */

#define	PACR		(CONFIG_MBAR + 0xc00)	/* PCI arbiter control */
#define	PASR		(CONFIG_MBAR + 0xc04)	/* PCI arbiter status */

/*
 *	Definitions for the Global status and control register.
 */
#define	PCIGSCR_PE	0x20000000		/* Parity error detected */
#define	PCIGSCR_SE	0x10000000		/* System error detected */
#define	PCIGSCR_XCLKBIN	0x07000000		/* XLB2CLKIN mask */
#define	PCIGSCR_PEE	0x00002000		/* Parity error intr enable */
#define	PCIGSCR_SEE	0x00001000		/* System error intr enable */
#define	PCIGSCR_RESET	0x00000001		/* Reset bit */

/*
 *	Bit definitions for the PCICAR configuration address register.
 */
#define	PCICAR_E	0x80000000		/* Enable config space */
#define	PCICAR_BUSN	16			/* Move bus bits */
#define	PCICAR_DEVFNN	8			/* Move devfn bits */
#define	PCICAR_DWORDN	0			/* Move dword bits */

/*
 *	The initiator windows hold the memory and IO mapping information.
 *	This macro creates the register values from the desired addresses.
 */
#define	WXBTAR(hostaddr, pciaddr, size)	\
			(((hostaddr) & 0xff000000) | \
			((((size) - 1) & 0xff000000) >> 8) | \
			(((pciaddr) & 0xff000000) >> 16))

#define	PCIIWCR_W0_MEM	0x00000000		/* Window 0 is memory */
#define	PCIIWCR_W0_IO	0x08000000		/* Window 0 is IO */
#define	PCIIWCR_W0_MRD	0x00000000		/* Window 0 memory read */
#define	PCIIWCR_W0_MRDL	0x02000000		/* Window 0 memory read line */
#define	PCIIWCR_W0_MRDM	0x04000000		/* Window 0 memory read mult */
#define	PCIIWCR_W0_E	0x01000000		/* Window 0 enable */

#define	PCIIWCR_W1_MEM	0x00000000		/* Window 0 is memory */
#define	PCIIWCR_W1_IO	0x00080000		/* Window 0 is IO */
#define	PCIIWCR_W1_MRD	0x00000000		/* Window 0 memory read */
#define	PCIIWCR_W1_MRDL	0x00020000		/* Window 0 memory read line */
#define	PCIIWCR_W1_MRDM	0x00040000		/* Window 0 memory read mult */
#define	PCIIWCR_W1_E	0x00010000		/* Window 0 enable */

/*
 *	Bit definitions for the PCIBATR registers.
 */
#define	PCITBATR0_E	0x00000001		/* Enable window 0 */
#define	PCITBATR1_E	0x00000001		/* Enable window 1 */

/*
 *	PCI arbiter support definitions and macros.
 */
#define	PACR_INTMPRI	0x00000001
#define	PACR_EXTMPRI(x)	(((x) & 0x1f) << 1)
#define	PACR_INTMINTE	0x00010000
#define	PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
#define	PACR_PKMD	0x40000000
#define	PACR_DS		0x80000000

#define	PCICR1_CL(x)	((x) & 0xf)		/* Cacheline size field */
#define	PCICR1_LT(x)	(((x) & 0xff) << 8)	/* Latency timer field */

/****************************************************************************/
#endif	/* M54XXPCI_H */

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