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/usr/src/linux-headers-5.15.0-190/arch/microblaze/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/microblaze/include/asm

Name	Size	Mode	Actions
asm-compat.h	518	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
barrier.h	313	0644	edit dl rm
cache.h	510	0644	edit dl rm
cacheflush.h	3209	0644	edit dl rm
checksum.h	806	0644	edit dl rm
cpuinfo.h	2043	0644	edit dl rm
current.h	714	0644	edit dl rm
delay.h	2138	0644	edit dl rm
dma.h	432	0644	edit dl rm
elf.h	602	0644	edit dl rm
entry.h	1018	0644	edit dl rm
exceptions.h	1928	0644	edit dl rm
fixmap.h	1874	0644	edit dl rm
flat.h	1982	0644	edit dl rm
ftrace.h	642	0644	edit dl rm
futex.h	2179	0644	edit dl rm
hash.h	2429	0644	edit dl rm
highmem.h	1800	0644	edit dl rm
io.h	1691	0644	edit dl rm
irq.h	376	0644	edit dl rm
irqflags.h	2529	0644	edit dl rm
Kbuild	250	0644	edit dl rm
kgdb.h	739	0644	edit dl rm
mmu.h	4050	0644	edit dl rm
mmu_context.h	72	0644	edit dl rm
mmu_context_mm.h	3893	0644	edit dl rm
module.h	704	0644	edit dl rm
page.h	4076	0644	edit dl rm
pci-bridge.h	4473	0644	edit dl rm
pci.h	1986	0644	edit dl rm
pgalloc.h	1042	0644	edit dl rm
pgtable.h	14526	0644	edit dl rm
processor.h	2693	0644	edit dl rm
ptrace.h	591	0644	edit dl rm
pvr.h	8791	0644	edit dl rm
registers.h	1508	0644	edit dl rm
seccomp.h	256	0644	edit dl rm
sections.h	501	0644	edit dl rm
setup.h	823	0644	edit dl rm
string.h	494	0644	edit dl rm
switch_to.h	493	0644	edit dl rm
syscall.h	2346	0644	edit dl rm
thread_info.h	3979	0644	edit dl rm
timex.h	266	0644	edit dl rm
tlbflush.h	1579	0644	edit dl rm
uaccess.h	8121	0644	edit dl rm
unistd.h	1051	0644	edit dl rm
unwind.h	611	0644	edit dl rm
vmalloc.h	108	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/microblaze/include/asm/cacheflush.h (3209B)

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
 * based on v850 version which was
 * Copyright (C) 2001,02,03 NEC Electronics Corporation
 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
 */

#ifndef _ASM_MICROBLAZE_CACHEFLUSH_H
#define _ASM_MICROBLAZE_CACHEFLUSH_H

/* Somebody depends on this; sigh... */
#include <linux/mm.h>
#include <linux/io.h>

/* Look at Documentation/core-api/cachetlb.rst */

/*
 * Cache handling functions.
 * Microblaze has a write-through data cache, meaning that the data cache
 * never needs to be flushed.  The only flushing operations that are
 * implemented are to invalidate the instruction cache.  These are called
 * after loading a user application into memory, we must invalidate the
 * instruction cache to make sure we don't fetch old, bad code.
 */

/* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate,
 * suffix r = range */
struct scache {
	/* icache */
	void (*ie)(void); /* enable */
	void (*id)(void); /* disable */
	void (*ifl)(void); /* flush */
	void (*iflr)(unsigned long a, unsigned long b);
	void (*iin)(void); /* invalidate */
	void (*iinr)(unsigned long a, unsigned long b);
	/* dcache */
	void (*de)(void); /* enable */
	void (*dd)(void); /* disable */
	void (*dfl)(void); /* flush */
	void (*dflr)(unsigned long a, unsigned long b);
	void (*din)(void); /* invalidate */
	void (*dinr)(unsigned long a, unsigned long b);
};

/* microblaze cache */
extern struct scache *mbc;

void microblaze_cache_init(void);

#define enable_icache()					mbc->ie();
#define disable_icache()				mbc->id();
#define flush_icache()					mbc->ifl();
#define flush_icache_range(start, end)			mbc->iflr(start, end);
#define invalidate_icache()				mbc->iin();
#define invalidate_icache_range(start, end)		mbc->iinr(start, end);

#define enable_dcache()					mbc->de();
#define disable_dcache()				mbc->dd();
/* FIXME for LL-temac driver */
#define invalidate_dcache()				mbc->din();
#define invalidate_dcache_range(start, end)		mbc->dinr(start, end);
#define flush_dcache()					mbc->dfl();
#define flush_dcache_range(start, end)			mbc->dflr(start, end);

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
/* MS: We have to implement it because of rootfs-jffs2 issue on WB */
#define flush_dcache_page(page) \
do { \
	unsigned long addr = (unsigned long) page_address(page); /* virtual */ \
	addr = (u32)virt_to_phys((void *)addr); \
	flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
} while (0);

#define flush_cache_page(vma, vmaddr, pfn) \
	flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE);

static inline void copy_to_user_page(struct vm_area_struct *vma,
				     struct page *page, unsigned long vaddr,
				     void *dst, void *src, int len)
{
	u32 addr = virt_to_phys(dst);
	memcpy(dst, src, len);
	if (vma->vm_flags & VM_EXEC) {
		invalidate_icache_range(addr, addr + PAGE_SIZE);
		flush_dcache_range(addr, addr + PAGE_SIZE);
	}
}
#define copy_to_user_page copy_to_user_page

#include <asm-generic/cacheflush.h>

#endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */

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