FM / asm

/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm

Name	Size	Mode	Actions
assembler.h	598	0644	edit dl rm
barrier.h	431	0644	edit dl rm
bitfield.h	47127	0644	edit dl rm
cache.h	276	0644	edit dl rm
cacheflush.h	1986	0644	edit dl rm
cache_info.h	315	0644	edit dl rm
current.h	304	0644	edit dl rm
delay.h	938	0644	edit dl rm
elf.h	6021	0644	edit dl rm
fixmap.h	831	0644	edit dl rm
fpu.h	3195	0644	edit dl rm
fpuemu.h	1272	0644	edit dl rm
ftrace.h	1161	0644	edit dl rm
futex.h	2483	0644	edit dl rm
highmem.h	1624	0644	edit dl rm
io.h	2474	0644	edit dl rm
irqflags.h	848	0644	edit dl rm
Kbuild	194	0644	edit dl rm
l2_cache.h	4791	0644	edit dl rm
linkage.h	264	0644	edit dl rm
memory.h	2713	0644	edit dl rm
mmu.h	213	0644	edit dl rm
mmu_context.h	1409	0644	edit dl rm
nds32.h	2018	0644	edit dl rm
nds32_fpu_inst.h	2510	0644	edit dl rm
page.h	1591	0644	edit dl rm
perf_event.h	445	0644	edit dl rm
pgalloc.h	1419	0644	edit dl rm
pgtable.h	11676	0644	edit dl rm
pmu.h	13350	0644	edit dl rm
proc-fns.h	1668	0644	edit dl rm
processor.h	2405	0644	edit dl rm
ptrace.h	1686	0644	edit dl rm
sfp-machine.h	4463	0644	edit dl rm
shmparam.h	462	0644	edit dl rm
stacktrace.h	884	0644	edit dl rm
string.h	471	0644	edit dl rm
suspend.h	258	0644	edit dl rm
swab.h	810	0644	edit dl rm
syscall.h	5496	0644	edit dl rm
syscalls.h	510	0644	edit dl rm
thread_info.h	2390	0644	edit dl rm
tlb.h	249	0644	edit dl rm
tlbflush.h	1144	0644	edit dl rm
uaccess.h	8272	0644	edit dl rm
unistd.h	156	0644	edit dl rm
vdso.h	429	0644	edit dl rm
vdso_datapage.h	1104	0644	edit dl rm
vdso_timer_info.h	357	0644	edit dl rm
vermagic.h	214	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/nds32/include/asm/l2_cache.h (4791B)

/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (C) 2005-2017 Andes Technology Corporation

#ifndef L2_CACHE_H
#define L2_CACHE_H

/* CCTL_CMD_OP */
#define L2_CA_CONF_OFF		0x0
#define L2_IF_CONF_OFF		0x4
#define L2CC_SETUP_OFF		0x8
#define L2CC_PROT_OFF		0xC
#define L2CC_CTRL_OFF		0x10
#define L2_INT_EN_OFF           0x20
#define L2_STA_OFF              0x24
#define RDERR_ADDR_OFF		0x28
#define WRERR_ADDR_OFF		0x2c
#define EVDPTERR_ADDR_OFF	0x30
#define IMPL3ERR_ADDR_OFF	0x34
#define L2_CNT0_CTRL_OFF        0x40
#define L2_EVNT_CNT0_OFF        0x44
#define L2_CNT1_CTRL_OFF        0x48
#define L2_EVNT_CNT1_OFF        0x4c
#define L2_CCTL_CMD_OFF		0x60
#define L2_CCTL_STATUS_OFF	0x64
#define L2_LINE_TAG_OFF		0x68
#define L2_LINE_DPT_OFF		0x70

#define CCTL_CMD_L2_IX_INVAL    0x0
#define CCTL_CMD_L2_PA_INVAL    0x1
#define CCTL_CMD_L2_IX_WB       0x2
#define CCTL_CMD_L2_PA_WB       0x3
#define CCTL_CMD_L2_PA_WBINVAL  0x5
#define CCTL_CMD_L2_SYNC        0xa

/* CCTL_CMD_TYPE */
#define CCTL_SINGLE_CMD         0
#define CCTL_BLOCK_CMD          0x10
#define CCTL_ALL_CMD		0x10

/******************************************************************************
 * L2_CA_CONF (Cache architecture configuration)
 *****************************************************************************/
#define L2_CA_CONF_offL2SET		0
#define L2_CA_CONF_offL2WAY		4
#define L2_CA_CONF_offL2CLSZ            8
#define L2_CA_CONF_offL2DW		11
#define L2_CA_CONF_offL2PT		14
#define L2_CA_CONF_offL2VER		16

#define L2_CA_CONF_mskL2SET	(0xFUL << L2_CA_CONF_offL2SET)
#define L2_CA_CONF_mskL2WAY	(0xFUL << L2_CA_CONF_offL2WAY)
#define L2_CA_CONF_mskL2CLSZ    (0x7UL << L2_CA_CONF_offL2CLSZ)
#define L2_CA_CONF_mskL2DW	(0x7UL << L2_CA_CONF_offL2DW)
#define L2_CA_CONF_mskL2PT	(0x3UL << L2_CA_CONF_offL2PT)
#define L2_CA_CONF_mskL2VER	(0xFFFFUL << L2_CA_CONF_offL2VER)

/******************************************************************************
 * L2CC_SETUP (L2CC Setup register)
 *****************************************************************************/
#define L2CC_SETUP_offPART              0
#define L2CC_SETUP_mskPART              (0x3UL << L2CC_SETUP_offPART)
#define L2CC_SETUP_offDDLATC            4
#define L2CC_SETUP_mskDDLATC            (0x3UL << L2CC_SETUP_offDDLATC)
#define L2CC_SETUP_offTDLATC            8
#define L2CC_SETUP_mskTDLATC            (0x3UL << L2CC_SETUP_offTDLATC)

/******************************************************************************
 * L2CC_PROT (L2CC Protect register)
 *****************************************************************************/
#define L2CC_PROT_offMRWEN              31
#define L2CC_PROT_mskMRWEN      (0x1UL << L2CC_PROT_offMRWEN)

/******************************************************************************
 * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
 *****************************************************************************/
#define L2CC_CTRL_offEN                 31
#define L2CC_CTRL_mskEN                 (0x1UL << L2CC_CTRL_offEN)

/******************************************************************************
 * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
 *****************************************************************************/
#define L2_CCTL_STATUS_offCMD_COMP      31
#define L2_CCTL_STATUS_mskCMD_COMP      (0x1 << L2_CCTL_STATUS_offCMD_COMP)

extern void __iomem *atl2c_base;
#include <linux/smp.h>
#include <asm/io.h>
#include <asm/bitfield.h>

#define L2C_R_REG(offset)               readl(atl2c_base + offset)
#define L2C_W_REG(offset, value)        writel(value, atl2c_base + offset)

#define L2_CMD_RDY()    \
        do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0)

static inline unsigned long L2_CACHE_SET(void)
{
	return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
		      L2_CA_CONF_offL2SET);
}

static inline unsigned long L2_CACHE_WAY(void)
{
	return 1 +
	    ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
	     L2_CA_CONF_offL2WAY);
}

static inline unsigned long L2_CACHE_LINE_SIZE(void)
{

return 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
		     L2_CA_CONF_offL2CLSZ);
}

static inline unsigned long GET_L2CC_CTRL_CPU(unsigned long cpu)
{
	if (cpu == smp_processor_id())
		return L2C_R_REG(L2CC_CTRL_OFF);
	return L2C_R_REG(L2CC_CTRL_OFF + (cpu << 8));
}

static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val)
{
	if (cpu == smp_processor_id())
		L2C_W_REG(L2CC_CTRL_OFF, val);
	else
		L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val);
}

static inline unsigned long GET_L2CC_STATUS_CPU(unsigned long cpu)
{
	if (cpu == smp_processor_id())
		return L2C_R_REG(L2_CCTL_STATUS_OFF);
	return L2C_R_REG(L2_CCTL_STATUS_OFF + (cpu << 8));
}
#endif

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