FM / asm

/usr/src/linux-headers-5.15.0-190/arch/openrisc/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/openrisc/include/asm

Name	Size	Mode	Actions
bitops/	-	0755	rm
asm-offsets.h	35	0644	edit dl rm
atomic.h	3609	0644	edit dl rm
barrier.h	241	0644	edit dl rm
bitops.h	1326	0644	edit dl rm
cache.h	681	0644	edit dl rm
cacheflush.h	2204	0644	edit dl rm
cmpxchg.h	4056	0644	edit dl rm
cpuinfo.h	763	0644	edit dl rm
delay.h	463	0644	edit dl rm
elf.h	1860	0644	edit dl rm
fixmap.h	2596	0644	edit dl rm
futex.h	2293	0644	edit dl rm
io.h	833	0644	edit dl rm
irq.h	561	0644	edit dl rm
irqflags.h	659	0644	edit dl rm
Kbuild	238	0644	edit dl rm
linkage.h	557	0644	edit dl rm
mmu.h	521	0644	edit dl rm
mmu_context.h	1108	0644	edit dl rm
page.h	2288	0644	edit dl rm
pgalloc.h	1831	0644	edit dl rm
pgtable.h	12749	0644	edit dl rm
processor.h	2339	0644	edit dl rm
ptrace.h	3201	0644	edit dl rm
serial.h	928	0644	edit dl rm
setup.h	293	0644	edit dl rm
smp.h	822	0644	edit dl rm
spinlock.h	778	0644	edit dl rm
spinlock_types.h	188	0644	edit dl rm
spr.h	991	0644	edit dl rm
spr_defs.h	23252	0644	edit dl rm
string.h	324	0644	edit dl rm
syscall.h	1658	0644	edit dl rm
syscalls.h	969	0644	edit dl rm
thread_info.h	3787	0644	edit dl rm
time.h	627	0644	edit dl rm
timex.h	707	0644	edit dl rm
tlb.h	651	0644	edit dl rm
tlbflush.h	1844	0644	edit dl rm
uaccess.h	7985	0644	edit dl rm
unwinder.h	557	0644	edit dl rm
vmalloc.h	102	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/openrisc/include/asm/cacheflush.h (2204B)

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * OpenRISC Linux
 *
 * Linux architectural port borrowing liberally from similar works of
 * others.  All original copyrights apply as per the original source
 * declaration.
 *
 * OpenRISC implementation:
 * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
 * et al.
 */

#ifndef __ASM_CACHEFLUSH_H
#define __ASM_CACHEFLUSH_H

#include <linux/mm.h>

/*
 * Helper function for flushing or invalidating entire pages from data
 * and instruction caches. SMP needs a little extra work, since we need
 * to flush the pages on all cpus.
 */
extern void local_dcache_page_flush(struct page *page);
extern void local_icache_page_inv(struct page *page);

/*
 * Data cache flushing always happen on the local cpu. Instruction cache
 * invalidations need to be broadcasted to all other cpu in the system in
 * case of SMP configurations.
 */
#ifndef CONFIG_SMP
#define dcache_page_flush(page)      local_dcache_page_flush(page)
#define icache_page_inv(page)        local_icache_page_inv(page)
#else  /* CONFIG_SMP */
#define dcache_page_flush(page)      local_dcache_page_flush(page)
#define icache_page_inv(page)        smp_icache_page_inv(page)
extern void smp_icache_page_inv(struct page *page);
#endif /* CONFIG_SMP */

/*
 * Synchronizes caches. Whenever a cpu writes executable code to memory, this
 * should be called to make sure the processor sees the newly written code.
 */
static inline void sync_icache_dcache(struct page *page)
{
	if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
		dcache_page_flush(page);
	icache_page_inv(page);
}

/*
 * Pages with this bit set need not be flushed/invalidated, since
 * they have not changed since last flush. New pages start with
 * PG_arch_1 not set and are therefore dirty by default.
 */
#define PG_dc_clean                  PG_arch_1

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
static inline void flush_dcache_page(struct page *page)
{
	clear_bit(PG_dc_clean, &page->flags);
}

#define flush_icache_user_page(vma, page, addr, len)	\
do {							\
	if (vma->vm_flags & VM_EXEC)			\
		sync_icache_dcache(page);		\
} while (0)

#include <asm-generic/cacheflush.h>

#endif /* __ASM_CACHEFLUSH_H */

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