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/usr/src/linux-headers-5.15.0-190/arch/parisc/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/parisc/include/asm

Name	Size	Mode	Actions
agp.h	596	0644	edit dl rm
alternative.h	1954	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asmregs.h	2478	0644	edit dl rm
assembly.h	12496	0644	edit dl rm
atomic.h	5718	0644	edit dl rm
barrier.h	2563	0644	edit dl rm
bitops.h	5578	0644	edit dl rm
bug.h	2408	0644	edit dl rm
cache.h	2084	0644	edit dl rm
cacheflush.h	3773	0644	edit dl rm
checksum.h	4715	0644	edit dl rm
cmpxchg.h	3783	0644	edit dl rm
compat.h	3973	0644	edit dl rm
compat_ucontext.h	591	0644	edit dl rm
delay.h	533	0644	edit dl rm
dma-mapping.h	1012	0644	edit dl rm
dma.h	5849	0644	edit dl rm
dwarf.h	456	0644	edit dl rm
eisa_bus.h	492	0644	edit dl rm
eisa_eeprom.h	4318	0644	edit dl rm
elf.h	14381	0644	edit dl rm
fb.h	491	0644	edit dl rm
fixmap.h	1611	0644	edit dl rm
floppy.h	6193	0644	edit dl rm
ftrace.h	641	0644	edit dl rm
futex.h	2666	0644	edit dl rm
grfioctl.h	4090	0644	edit dl rm
hardirq.h	976	0644	edit dl rm
hardware.h	4239	0644	edit dl rm
hash.h	5194	0644	edit dl rm
hugetlb.h	1331	0644	edit dl rm
ide.h	1120	0644	edit dl rm
io.h	8307	0644	edit dl rm
irq.h	1171	0644	edit dl rm
irqflags.h	1046	0644	edit dl rm
jump_label.h	990	0644	edit dl rm
kbdleds.h	477	0644	edit dl rm
Kbuild	175	0644	edit dl rm
kexec.h	827	0644	edit dl rm
kgdb.h	1318	0644	edit dl rm
kprobes.h	1284	0644	edit dl rm
ldcw.h	2570	0644	edit dl rm
led.h	1362	0644	edit dl rm
linkage.h	738	0644	edit dl rm
machdep.h	349	0644	edit dl rm
mckinley.h	270	0644	edit dl rm
mmu.h	195	0644	edit dl rm
mmu_context.h	2355	0644	edit dl rm
mmzone.h	202	0644	edit dl rm
module.h	527	0644	edit dl rm
page.h	5533	0644	edit dl rm
parisc-device.h	1964	0644	edit dl rm
parport.h	358	0644	edit dl rm
patch.h	445	0644	edit dl rm
pci.h	5956	0644	edit dl rm
pdc.h	4269	0644	edit dl rm
pdcpat.h	16968	0644	edit dl rm
pdc_chassis.h	14745	0644	edit dl rm
perf.h	1936	0644	edit dl rm
perf_event.h	152	0644	edit dl rm
pgalloc.h	1722	0644	edit dl rm
pgtable.h	17062	0644	edit dl rm
prefetch.h	1147	0644	edit dl rm
processor.h	9486	0644	edit dl rm
psw.h	2464	0644	edit dl rm
ptrace.h	1603	0644	edit dl rm
ropes.h	10060	0644	edit dl rm
rt_sigframe.h	745	0644	edit dl rm
runway.h	320	0644	edit dl rm
seccomp.h	651	0644	edit dl rm
sections.h	494	0644	edit dl rm
serial.h	124	0644	edit dl rm
shmparam.h	263	0644	edit dl rm
signal.h	685	0644	edit dl rm
smp.h	1276	0644	edit dl rm
socket.h	310	0644	edit dl rm
sparsemem.h	345	0644	edit dl rm
special_insns.h	1554	0644	edit dl rm
spinlock.h	3182	0644	edit dl rm
spinlock_types.h	701	0644	edit dl rm
string.h	247	0644	edit dl rm
superio.h	3333	0644	edit dl rm
switch_to.h	332	0644	edit dl rm
syscall.h	1477	0644	edit dl rm
termios.h	1761	0644	edit dl rm
thread_info.h	3143	0644	edit dl rm
timex.h	403	0644	edit dl rm
tlb.h	288	0644	edit dl rm
tlbflush.h	1975	0644	edit dl rm
topology.h	900	0644	edit dl rm
traps.h	598	0644	edit dl rm
uaccess.h	6253	0644	edit dl rm
ucontext.h	327	0644	edit dl rm
unaligned.h	307	0644	edit dl rm
unistd.h	5776	0644	edit dl rm
unwind.h	2723	0644	edit dl rm
vmalloc.h	96	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/parisc/include/asm/pci.h (5956B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_PCI_H
#define __ASM_PARISC_PCI_H

#include <linux/scatterlist.h>

/*
** HP PCI platforms generally support multiple bus adapters.
**    (workstations 1-~4, servers 2-~32)
**
** Newer platforms number the busses across PCI bus adapters *sparsely*.
** E.g. 0, 8, 16, ...
**
** Under a PCI bus, most HP platforms support PPBs up to two or three
** levels deep. See "Bit3" product line. 
*/
#define PCI_MAX_BUSSES	256

/* To be used as: mdelay(pci_post_reset_delay);
 *
 * post_reset is the time the kernel should stall to prevent anyone from
 * accessing the PCI bus once #RESET is de-asserted. 
 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
 * this makes the boot time much longer than necessary.
 * 20ms seems to work for all the HP PCI implementations to date.
 */
#define pci_post_reset_delay 50

/*
** pci_hba_data (aka H2P_OBJECT in HP/UX)
**
** This is the "common" or "base" data structure which HBA drivers
** (eg Dino or LBA) are required to place at the top of their own
** platform_data structure.  I've heard this called "C inheritance" too.
**
** Data needed by pcibios layer belongs here.
*/
struct pci_hba_data {
	void __iomem   *base_addr;	/* aka Host Physical Address */
	const struct parisc_device *dev; /* device from PA bus walk */
	struct pci_bus *hba_bus;	/* primary PCI bus below HBA */
	int		hba_num;	/* I/O port space access "key" */
	struct resource bus_num;	/* PCI bus numbers */
	struct resource io_space;	/* PIOP */
	struct resource lmmio_space;	/* bus addresses < 4Gb */
	struct resource elmmio_space;	/* additional bus addresses < 4Gb */
	struct resource gmmio_space;	/* bus addresses > 4Gb */

/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
	 * elmmio_space and gmmio_space as a contiguous array of
	 * resources.  This #define represents the array size */
	#define DINO_MAX_LMMIO_RESOURCES	3

unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
	struct ioc	*iommu;		/* IOMMU this device is under */
	/* REVISIT - spinlock to protect resources? */

#define HBA_NAME_SIZE 16
	char io_name[HBA_NAME_SIZE];
	char lmmio_name[HBA_NAME_SIZE];
	char elmmio_name[HBA_NAME_SIZE];
	char gmmio_name[HBA_NAME_SIZE];
};

/* 
** We support 2^16 I/O ports per HBA.  These are set up in the form
** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
** space address.
*/
#define HBA_PORT_SPACE_BITS	16

#define HBA_PORT_BASE(h)	((h) << HBA_PORT_SPACE_BITS)
#define HBA_PORT_SPACE_SIZE	(1UL << HBA_PORT_SPACE_BITS)

#define PCI_PORT_HBA(a)		((a) >> HBA_PORT_SPACE_BITS)
#define PCI_PORT_ADDR(a)	((a) & (HBA_PORT_SPACE_SIZE - 1))

#ifdef CONFIG_64BIT
#define PCI_F_EXTEND		0xffffffff00000000UL
#else	/* !CONFIG_64BIT */
#define PCI_F_EXTEND		0UL
#endif /* !CONFIG_64BIT */

/*
** Most PCI devices (eg Tulip, NCR720) also export the same registers
** to both MMIO and I/O port space.  Due to poor performance of I/O Port
** access under HP PCI bus adapters, strongly recommend the use of MMIO
** address space.
**
** While I'm at it more PA programming notes:
**
** 1) MMIO stores (writes) are posted operations. This means the processor
**    gets an "ACK" before the write actually gets to the device. A read
**    to the same device (or typically the bus adapter above it) will
**    force in-flight write transaction(s) out to the targeted device
**    before the read can complete.
**
** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
**    respect to DMA on all platforms. Ie PIO data can reach the processor
**    before in-flight DMA reaches memory. Since most SMP PA platforms
**    are I/O coherent, it generally doesn't matter...but sometimes
**    it does.
**
** I've helped device driver writers debug both types of problems.
*/
struct pci_port_ops {
	  u8 (*inb)  (struct pci_hba_data *hba, u16 port);
	 u16 (*inw)  (struct pci_hba_data *hba, u16 port);
	 u32 (*inl)  (struct pci_hba_data *hba, u16 port);
	void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
	void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
	void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
};

struct pci_bios_ops {
	void (*init)(void);
	void (*fixup_bus)(struct pci_bus *bus);
};

/*
** Stuff declared in arch/parisc/kernel/pci.c
*/
extern struct pci_port_ops *pci_port;
extern struct pci_bios_ops *pci_bios;

#ifdef CONFIG_PCI
extern void pcibios_register_hba(struct pci_hba_data *);
#else
static inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif
extern void pcibios_init_bridge(struct pci_dev *);

/*
 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
 *   0 == check if bridge is numbered before re-numbering.
 *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
 *
 *   We *should* set this to zero for "legacy" platforms and one
 *   for PAT platforms.
 *
 *   But legacy platforms also need to renumber the busses below a Host
 *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
 *   bus of a C200 resulted in the secondary bus being numbered as 1.
 *   The second PCI host bus controller's root bus had already been
 *   assigned bus number 1 by firmware and sysfs complained.
 *
 *   Firmware isn't doing anything wrong here since each controller
 *   is its own PCI domain.  It's simpler and easier for us to renumber
 *   the busses rather than treat each Dino as a separate PCI domain.
 *   Eventually, we may want to introduce PCI domains for Superdome or
 *   rp7420/8420 boxes and then revisit this issue.
 */
#define pcibios_assign_all_busses()     (1)

#define PCIBIOS_MIN_IO          0x10
#define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */

static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE

#endif /* __ASM_PARISC_PCI_H */

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