FM / asm

/usr/src/linux-headers-5.15.0-190/arch/riscv/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/riscv/include/asm

Name	Size	Mode	Actions
vdso/	-	0755	rm
alternative-macros.h	4658	0644	edit dl rm
alternative.h	930	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	1040	0644	edit dl rm
asm.h	1558	0644	edit dl rm
atomic.h	11028	0644	edit dl rm
barrier.h	2458	0644	edit dl rm
bitops.h	5809	0644	edit dl rm
bug.h	2186	0644	edit dl rm
cache.h	516	0644	edit dl rm
cacheflush.h	1399	0644	edit dl rm
cacheinfo.h	511	0644	edit dl rm
clint.h	797	0644	edit dl rm
clocksource.h	136	0644	edit dl rm
cmpxchg.h	9537	0644	edit dl rm
cpu_ops.h	1494	0644	edit dl rm
csr.h	6062	0644	edit dl rm
current.h	940	0644	edit dl rm
delay.h	471	0644	edit dl rm
efi.h	1150	0644	edit dl rm
elf.h	2726	0644	edit dl rm
errata_list.h	1074	0644	edit dl rm
fence.h	279	0644	edit dl rm
fixmap.h	1806	0644	edit dl rm
ftrace.h	3086	0644	edit dl rm
futex.h	2906	0644	edit dl rm
gdb_xml.h	5601	0644	edit dl rm
hugetlb.h	360	0644	edit dl rm
hwcap.h	1245	0644	edit dl rm
image.h	1673	0644	edit dl rm
io.h	5322	0644	edit dl rm
irq.h	347	0644	edit dl rm
irqflags.h	1175	0644	edit dl rm
irq_work.h	225	0644	edit dl rm
jump_label.h	1440	0644	edit dl rm
kasan.h	1390	0644	edit dl rm
Kbuild	178	0644	edit dl rm
kdebug.h	158	0644	edit dl rm
kexec.h	1349	0644	edit dl rm
kfence.h	1312	0644	edit dl rm
kgdb.h	2494	0644	edit dl rm
kprobes.h	1136	0644	edit dl rm
linkage.h	267	0644	edit dl rm
mmio.h	5347	0644	edit dl rm
mmiowb.h	398	0644	edit dl rm
mmu.h	610	0644	edit dl rm
mmu_context.h	898	0644	edit dl rm
mmzone.h	266	0644	edit dl rm
module.h	2984	0644	edit dl rm
module.lds.h	207	0644	edit dl rm
numa.h	165	0644	edit dl rm
page.h	5264	0644	edit dl rm
parse_asm.h	7265	0644	edit dl rm
patch.h	314	0644	edit dl rm
pci.h	1062	0644	edit dl rm
perf_event.h	2204	0644	edit dl rm
pgalloc.h	1801	0644	edit dl rm
pgtable-32.h	498	0644	edit dl rm
pgtable-64.h	1898	0644	edit dl rm
pgtable-bits.h	1552	0644	edit dl rm
pgtable.h	18086	0644	edit dl rm
probes.h	563	0644	edit dl rm
processor.h	2138	0644	edit dl rm
ptdump.h	338	0644	edit dl rm
ptrace.h	4304	0644	edit dl rm
sbi.h	4223	0644	edit dl rm
seccomp.h	504	0644	edit dl rm
sections.h	883	0644	edit dl rm
set_memory.h	1869	0644	edit dl rm
smp.h	2427	0644	edit dl rm
soc.h	627	0644	edit dl rm
sparsemem.h	263	0644	edit dl rm
spinlock.h	2508	0644	edit dl rm
spinlock_types.h	530	0644	edit dl rm
stackprotector.h	768	0644	edit dl rm
stacktrace.h	496	0644	edit dl rm
string.h	1078	0644	edit dl rm
switch_to.h	2107	0644	edit dl rm
syscall.h	2163	0644	edit dl rm
thread_info.h	3955	0644	edit dl rm
timex.h	1859	0644	edit dl rm
tlb.h	403	0644	edit dl rm
tlbflush.h	1803	0644	edit dl rm
uaccess.h	13955	0644	edit dl rm
unistd.h	328	0644	edit dl rm
uprobes.h	828	0644	edit dl rm
vdso.h	868	0644	edit dl rm
vendorid_list.h	172	0644	edit dl rm
vermagic.h	213	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm
word-at-a-time.h	1104	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/riscv/include/asm/csr.h (6062B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2015 Regents of the University of California
 */

#ifndef _ASM_RISCV_CSR_H
#define _ASM_RISCV_CSR_H

#include <asm/asm.h>
#include <linux/const.h>

/* Status register flags */
#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
#define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */

#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF	_AC(0x00000000, UL)
#define SR_FS_INITIAL	_AC(0x00002000, UL)
#define SR_FS_CLEAN	_AC(0x00004000, UL)
#define SR_FS_DIRTY	_AC(0x00006000, UL)

#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF	_AC(0x00000000, UL)
#define SR_XS_INITIAL	_AC(0x00008000, UL)
#define SR_XS_CLEAN	_AC(0x00010000, UL)
#define SR_XS_DIRTY	_AC(0x00018000, UL)

#ifndef CONFIG_64BIT
#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
#else
#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
#endif

/* SATP flags */
#ifndef CONFIG_64BIT
#define SATP_PPN	_AC(0x003FFFFF, UL)
#define SATP_MODE_32	_AC(0x80000000, UL)
#define SATP_MODE	SATP_MODE_32
#define SATP_ASID_BITS	9
#define SATP_ASID_SHIFT	22
#define SATP_ASID_MASK	_AC(0x1FF, UL)
#else
#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
#define SATP_MODE_39	_AC(0x8000000000000000, UL)
#define SATP_MODE	SATP_MODE_39
#define SATP_ASID_BITS	16
#define SATP_ASID_SHIFT	44
#define SATP_ASID_MASK	_AC(0xFFFF, UL)
#endif

/* Exception cause high bit - is an interrupt if set */
#define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))

/* Interrupt causes (minus the high bit) */
#define IRQ_S_SOFT		1
#define IRQ_M_SOFT		3
#define IRQ_S_TIMER		5
#define IRQ_M_TIMER		7
#define IRQ_S_EXT		9
#define IRQ_M_EXT		11

/* Exception causes */
#define EXC_INST_MISALIGNED	0
#define EXC_INST_ACCESS		1
#define EXC_BREAKPOINT		3
#define EXC_LOAD_ACCESS		5
#define EXC_STORE_ACCESS	7
#define EXC_SYSCALL		8
#define EXC_INST_PAGE_FAULT	12
#define EXC_LOAD_PAGE_FAULT	13
#define EXC_STORE_PAGE_FAULT	15

/* PMP configuration */
#define PMP_R			0x01
#define PMP_W			0x02
#define PMP_X			0x04
#define PMP_A			0x18
#define PMP_A_TOR		0x08
#define PMP_A_NA4		0x10
#define PMP_A_NAPOT		0x18
#define PMP_L			0x80

/* symbolic CSR names: */
#define CSR_CYCLE		0xc00
#define CSR_TIME		0xc01
#define CSR_INSTRET		0xc02
#define CSR_CYCLEH		0xc80
#define CSR_TIMEH		0xc81
#define CSR_INSTRETH		0xc82

#define CSR_SSTATUS		0x100
#define CSR_SIE			0x104
#define CSR_STVEC		0x105
#define CSR_SCOUNTEREN		0x106
#define CSR_SSCRATCH		0x140
#define CSR_SEPC		0x141
#define CSR_SCAUSE		0x142
#define CSR_STVAL		0x143
#define CSR_SIP			0x144
#define CSR_SATP		0x180

#define CSR_MSTATUS		0x300
#define CSR_MISA		0x301
#define CSR_MIE			0x304
#define CSR_MTVEC		0x305
#define CSR_MSCRATCH		0x340
#define CSR_MEPC		0x341
#define CSR_MCAUSE		0x342
#define CSR_MTVAL		0x343
#define CSR_MIP			0x344
#define CSR_PMPCFG0		0x3a0
#define CSR_PMPADDR0		0x3b0
#define CSR_MVENDORID		0xf11
#define CSR_MARCHID		0xf12
#define CSR_MIMPID		0xf13
#define CSR_MHARTID		0xf14

#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS	CSR_MSTATUS
# define CSR_IE		CSR_MIE
# define CSR_TVEC	CSR_MTVEC
# define CSR_SCRATCH	CSR_MSCRATCH
# define CSR_EPC	CSR_MEPC
# define CSR_CAUSE	CSR_MCAUSE
# define CSR_TVAL	CSR_MTVAL
# define CSR_IP		CSR_MIP

# define SR_IE		SR_MIE
# define SR_PIE		SR_MPIE
# define SR_PP		SR_MPP

# define RV_IRQ_SOFT		IRQ_M_SOFT
# define RV_IRQ_TIMER	IRQ_M_TIMER
# define RV_IRQ_EXT		IRQ_M_EXT
#else /* CONFIG_RISCV_M_MODE */
# define CSR_STATUS	CSR_SSTATUS
# define CSR_IE		CSR_SIE
# define CSR_TVEC	CSR_STVEC
# define CSR_SCRATCH	CSR_SSCRATCH
# define CSR_EPC	CSR_SEPC
# define CSR_CAUSE	CSR_SCAUSE
# define CSR_TVAL	CSR_STVAL
# define CSR_IP		CSR_SIP

# define SR_IE		SR_SIE
# define SR_PIE		SR_SPIE
# define SR_PP		SR_SPP

# define RV_IRQ_SOFT		IRQ_S_SOFT
# define RV_IRQ_TIMER	IRQ_S_TIMER
# define RV_IRQ_EXT		IRQ_S_EXT
#endif /* CONFIG_RISCV_M_MODE */

/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
#define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
#define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)

#ifndef __ASSEMBLY__

#define csr_swap(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_read(csr)						\
({								\
	register unsigned long __v;				\
	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
			      : "=r" (__v) :			\
			      : "memory");			\
	__v;							\
})

#define csr_write(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#define csr_read_set(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_set(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#define csr_read_clear(csr, val)				\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
			      : "=r" (__v) : "rK" (__v)		\
			      : "memory");			\
	__v;							\
})

#define csr_clear(csr, val)					\
({								\
	unsigned long __v = (unsigned long)(val);		\
	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
			      : : "rK" (__v)			\
			      : "memory");			\
})

#endif /* __ASSEMBLY__ */

#endif /* _ASM_RISCV_CSR_H */

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