FM / asm

/usr/src/linux-headers-5.15.0-190/arch/sh/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/sh/include/asm

Name	Size	Mode	Actions
adc.h	211	0644	edit dl rm
addrspace.h	1896	0644	edit dl rm
alignment.h	654	0644	edit dl rm
asm-offsets.h	74	0644	edit dl rm
atomic-grb.h	2677	0644	edit dl rm
atomic-irq.h	1687	0644	edit dl rm
atomic-llsc.h	2186	0644	edit dl rm
atomic.h	840	0644	edit dl rm
barrier.h	1503	0644	edit dl rm
bitops-cas.h	1770	0644	edit dl rm
bitops-grb.h	6364	0644	edit dl rm
bitops-llsc.h	2858	0644	edit dl rm
bitops-op32.h	3842	0644	edit dl rm
bitops.h	1653	0644	edit dl rm
bl_bit.h	66	0644	edit dl rm
bl_bit_32.h	639	0644	edit dl rm
bug.h	2835	0644	edit dl rm
cache.h	1171	0644	edit dl rm
cacheflush.h	3735	0644	edit dl rm
cache_insns.h	71	0644	edit dl rm
cache_insns_32.h	642	0644	edit dl rm
checksum.h	68	0644	edit dl rm
checksum_32.h	5009	0644	edit dl rm
clock.h	436	0644	edit dl rm
cmpxchg-cas.h	549	0644	edit dl rm
cmpxchg-grb.h	2869	0644	edit dl rm
cmpxchg-irq.h	1065	0644	edit dl rm
cmpxchg-llsc.h	1085	0644	edit dl rm
cmpxchg-xchg.h	1274	0644	edit dl rm
cmpxchg.h	1822	0644	edit dl rm
device.h	442	0644	edit dl rm
dma-register.h	1708	0644	edit dl rm
dma.h	3652	0644	edit dl rm
dmabrg.h	536	0644	edit dl rm
dwarf.h	9896	0644	edit dl rm
elf.h	6009	0644	edit dl rm
entry-macros.S	1897	0644	edit dl rm
extable.h	135	0644	edit dl rm
fb.h	414	0644	edit dl rm
fixmap.h	2543	0644	edit dl rm
flat.h	863	0644	edit dl rm
fpu.h	1635	0644	edit dl rm
freq.h	212	0644	edit dl rm
ftrace.h	1138	0644	edit dl rm
futex-cas.h	728	0644	edit dl rm
futex-irq.h	482	0644	edit dl rm
futex-llsc.h	870	0644	edit dl rm
futex.h	1381	0644	edit dl rm
gpio.h	851	0644	edit dl rm
hardirq.h	267	0644	edit dl rm
hd64461.h	12068	0644	edit dl rm
heartbeat.h	383	0644	edit dl rm
hugetlb.h	915	0644	edit dl rm
hw_breakpoint.h	1970	0644	edit dl rm
hw_irq.h	915	0644	edit dl rm
i2c-sh7760.h	406	0644	edit dl rm
io.h	8699	0644	edit dl rm
io_generic.h	661	0644	edit dl rm
io_noioport.h	1502	0644	edit dl rm
io_trapped.h	1474	0644	edit dl rm
irq.h	1642	0644	edit dl rm
irqflags.h	226	0644	edit dl rm
Kbuild	141	0644	edit dl rm
kdebug.h	433	0644	edit dl rm
kexec.h	2672	0644	edit dl rm
kgdb.h	851	0644	edit dl rm
kprobes.h	1407	0644	edit dl rm
linkage.h	154	0644	edit dl rm
machvec.h	850	0644	edit dl rm
mmiowb.h	246	0644	edit dl rm
mmu.h	2231	0644	edit dl rm
mmu_context.h	4167	0644	edit dl rm
mmu_context_32.h	1136	0644	edit dl rm
mmzone.h	1052	0644	edit dl rm
module.h	276	0644	edit dl rm
page.h	5419	0644	edit dl rm
pci.h	3007	0644	edit dl rm
perf_event.h	797	0644	edit dl rm
pgalloc.h	1107	0644	edit dl rm
pgtable-2level.h	567	0644	edit dl rm
pgtable-3level.h	1464	0644	edit dl rm
pgtable.h	4305	0644	edit dl rm
pgtable_32.h	15899	0644	edit dl rm
platform_early.h	1850	0644	edit dl rm
posix_types.h	71	0644	edit dl rm
processor.h	4342	0644	edit dl rm
processor_32.h	4614	0644	edit dl rm
ptrace.h	3834	0644	edit dl rm
ptrace_32.h	307	0644	edit dl rm
push-switch.h	755	0644	edit dl rm
reboot.h	472	0644	edit dl rm
romimage-macros.h	1126	0644	edit dl rm
rtc.h	249	0644	edit dl rm
seccomp.h	546	0644	edit dl rm
sections.h	311	0644	edit dl rm
segment.h	860	0644	edit dl rm
setup.h	725	0644	edit dl rm
sfp-machine.h	2767	0644	edit dl rm
sh7760fb.h	5740	0644	edit dl rm
shmparam.h	489	0644	edit dl rm
sh_bios.h	743	0644	edit dl rm
siu.h	385	0644	edit dl rm
smc37c93x.h	5698	0644	edit dl rm
smp-ops.h	1012	0644	edit dl rm
smp.h	1847	0644	edit dl rm
sparsemem.h	319	0644	edit dl rm
spi.h	265	0644	edit dl rm
spinlock-cas.h	2001	0644	edit dl rm
spinlock-llsc.h	4149	0644	edit dl rm
spinlock.h	438	0644	edit dl rm
spinlock_types.h	463	0644	edit dl rm
sram.h	670	0644	edit dl rm
stackprotector.h	711	0644	edit dl rm
stacktrace.h	528	0644	edit dl rm
string.h	66	0644	edit dl rm
string_32.h	2208	0644	edit dl rm
suspend.h	2576	0644	edit dl rm
switch_to.h	190	0644	edit dl rm
switch_to_32.h	3631	0644	edit dl rm
syscall.h	201	0644	edit dl rm
syscalls.h	454	0644	edit dl rm
syscalls_32.h	979	0644	edit dl rm
syscall_32.h	1917	0644	edit dl rm
thread_info.h	5342	0644	edit dl rm
timex.h	637	0644	edit dl rm
tlb.h	625	0644	edit dl rm
tlbflush.h	1809	0644	edit dl rm
topology.h	645	0644	edit dl rm
traps.h	424	0644	edit dl rm
traps_32.h	1338	0644	edit dl rm
types.h	326	0644	edit dl rm
uaccess.h	4811	0644	edit dl rm
uaccess_32.h	5007	0644	edit dl rm
uncached.h	1372	0644	edit dl rm
unistd.h	919	0644	edit dl rm
unwinder.h	856	0644	edit dl rm
user.h	2440	0644	edit dl rm
vermagic.h	709	0644	edit dl rm
vga.h	137	0644	edit dl rm
vmalloc.h	84	0644	edit dl rm
vmlinux.lds.h	416	0644	edit dl rm
watchdog.h	3981	0644	edit dl rm
word-at-a-time.h	1321	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/sh/include/asm/io.h (8699B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H

/*
 * Convention:
 *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
 *    while in{b,w,l}/out{b,w,l} are for ISA
 *
 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
 *
 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
 * automatically, there are also __raw versions, which do not.
 */
#include <linux/errno.h>
#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/machvec.h>
#include <asm/page.h>
#include <linux/pgtable.h>
#include <asm-generic/iomap.h>

#define __IO_PREFIX     generic
#include <asm/io_generic.h>
#include <asm-generic/pci_iomap.h>
#include <mach/mangle-port.h>

#define __raw_writeb(v,a)	(__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
#define __raw_writew(v,a)	(__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
#define __raw_writel(v,a)	(__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
#define __raw_writeq(v,a)	(__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))

#define __raw_readb(a)		(__chk_io_ptr(a), *(volatile u8  __force *)(a))
#define __raw_readw(a)		(__chk_io_ptr(a), *(volatile u16 __force *)(a))
#define __raw_readl(a)		(__chk_io_ptr(a), *(volatile u32 __force *)(a))
#define __raw_readq(a)		(__chk_io_ptr(a), *(volatile u64 __force *)(a))

#define readb_relaxed(c)	({ u8  __v = ioswabb(__raw_readb(c)); __v; })
#define readw_relaxed(c)	({ u16 __v = ioswabw(__raw_readw(c)); __v; })
#define readl_relaxed(c)	({ u32 __v = ioswabl(__raw_readl(c)); __v; })
#define readq_relaxed(c)	({ u64 __v = ioswabq(__raw_readq(c)); __v; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((__force  u8)ioswabb(v),c))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)ioswabw(v),c))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)ioswabl(v),c))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)ioswabq(v),c))

#define readb(a)		({ u8  r_ = readb_relaxed(a); rmb(); r_; })
#define readw(a)		({ u16 r_ = readw_relaxed(a); rmb(); r_; })
#define readl(a)		({ u32 r_ = readl_relaxed(a); rmb(); r_; })
#define readq(a)		({ u64 r_ = readq_relaxed(a); rmb(); r_; })

#define writeb(v,a)		({ wmb(); writeb_relaxed((v),(a)); })
#define writew(v,a)		({ wmb(); writew_relaxed((v),(a)); })
#define writel(v,a)		({ wmb(); writel_relaxed((v),(a)); })
#define writeq(v,a)		({ wmb(); writeq_relaxed((v),(a)); })

#define readsb(p,d,l)		__raw_readsb(p,d,l)
#define readsw(p,d,l)		__raw_readsw(p,d,l)
#define readsl(p,d,l)		__raw_readsl(p,d,l)

#define writesb(p,d,l)		__raw_writesb(p,d,l)
#define writesw(p,d,l)		__raw_writesw(p,d,l)
#define writesl(p,d,l)		__raw_writesl(p,d,l)

#define __BUILD_UNCACHED_IO(bwlq, type)					\
static inline type read##bwlq##_uncached(unsigned long addr)		\
{									\
	type ret;							\
	jump_to_uncached();						\
	ret = __raw_read##bwlq(addr);					\
	back_to_cached();						\
	return ret;							\
}									\
									\
static inline void write##bwlq##_uncached(type v, unsigned long addr)	\
{									\
	jump_to_uncached();						\
	__raw_write##bwlq(v, addr);					\
	back_to_cached();						\
}

__BUILD_UNCACHED_IO(b, u8)
__BUILD_UNCACHED_IO(w, u16)
__BUILD_UNCACHED_IO(l, u32)
__BUILD_UNCACHED_IO(q, u64)

#define __BUILD_MEMORY_STRING(pfx, bwlq, type)				\
									\
static inline void							\
pfx##writes##bwlq(volatile void __iomem *mem, const void *addr,		\
		  unsigned int count)					\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__raw_write##bwlq(*__addr, mem);			\
		__addr++;						\
	}								\
}									\
									\
static inline void pfx##reads##bwlq(volatile void __iomem *mem,		\
				    void *addr, unsigned int count)	\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __raw_read##bwlq(mem);			\
		__addr++;						\
	}								\
}

__BUILD_MEMORY_STRING(__raw_, b, u8)
__BUILD_MEMORY_STRING(__raw_, w, u16)

void __raw_writesl(void __iomem *addr, const void *data, int longlen);
void __raw_readsl(const void __iomem *addr, void *data, int longlen);

__BUILD_MEMORY_STRING(__raw_, q, u64)

#ifdef CONFIG_HAS_IOPORT_MAP

/*
 * Slowdown I/O port space accesses for antique hardware.
 */
#undef CONF_SLOWDOWN_IO

/*
 * On SuperH I/O ports are memory mapped, so we access them using normal
 * load/store instructions. sh_io_port_base is the virtual address to
 * which all ports are being mapped.
 */
extern unsigned long sh_io_port_base;

static inline void __set_io_port_base(unsigned long pbase)
{
	*(unsigned long *)&sh_io_port_base = pbase;
	barrier();
}

#ifdef CONFIG_GENERIC_IOMAP
#define __ioport_map ioport_map
#else
extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
#endif

#ifdef CONF_SLOWDOWN_IO
#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
#else
#define SLOW_DOWN_IO
#endif

#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)			\
									\
static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
{									\
	volatile type *__addr;						\
									\
	__addr = __ioport_map(port, sizeof(type));			\
	*__addr = val;							\
	slow;								\
}									\
									\
static inline type pfx##in##bwlq##p(unsigned long port)			\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	__addr = __ioport_map(port, sizeof(type));			\
	__val = *__addr;						\
	slow;								\
									\
	return __val;							\
}

#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)			\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)

#define BUILDIO_IOPORT(bwlq, type)					\
	__BUILD_IOPORT_PFX(, bwlq, type)

BUILDIO_IOPORT(b, u8)
BUILDIO_IOPORT(w, u16)
BUILDIO_IOPORT(l, u32)
BUILDIO_IOPORT(q, u64)

#define __BUILD_IOPORT_STRING(bwlq, type)				\
									\
static inline void outs##bwlq(unsigned long port, const void *addr,	\
			      unsigned int count)			\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		out##bwlq(*__addr, port);				\
		__addr++;						\
	}								\
}									\
									\
static inline void ins##bwlq(unsigned long port, void *addr,		\
			     unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = in##bwlq(port);				\
		__addr++;						\
	}								\
}

__BUILD_IOPORT_STRING(b, u8)
__BUILD_IOPORT_STRING(w, u16)
__BUILD_IOPORT_STRING(l, u32)
__BUILD_IOPORT_STRING(q, u64)

#else /* !CONFIG_HAS_IOPORT_MAP */

#include <asm/io_noioport.h>

#endif

#define IO_SPACE_LIMIT 0xffffffff

/* We really want to try and get these to memcpy etc */
void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
void memset_io(volatile void __iomem *, int, unsigned long);

/* Quad-word real-mode I/O, don't ask.. */
unsigned long long peek_real_address_q(unsigned long long addr);
unsigned long long poke_real_address_q(unsigned long long addr,
				       unsigned long long val);

#if !defined(CONFIG_MMU)
#define virt_to_phys(address)	((unsigned long)(address))
#define phys_to_virt(address)	((void *)(address))
#else
#define virt_to_phys(address)	(__pa(address))
#define phys_to_virt(address)	(__va(address))
#endif

#ifdef CONFIG_MMU
void iounmap(void __iomem *addr);
void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
			       pgprot_t prot, void *caller);

static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
{
	return __ioremap_caller(offset, size, PAGE_KERNEL_NOCACHE,
			__builtin_return_address(0));
}

static inline void __iomem *
ioremap_cache(phys_addr_t offset, unsigned long size)
{
	return __ioremap_caller(offset, size, PAGE_KERNEL,
			__builtin_return_address(0));
}
#define ioremap_cache ioremap_cache

#ifdef CONFIG_HAVE_IOREMAP_PROT
static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
		unsigned long flags)
{
	return __ioremap_caller(offset, size, __pgprot(flags),
			__builtin_return_address(0));
}
#endif /* CONFIG_HAVE_IOREMAP_PROT */

#else /* CONFIG_MMU */
static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
{
	return (void __iomem *)(unsigned long)offset;
}

static inline void iounmap(volatile void __iomem *addr) { }
#endif /* CONFIG_MMU */

#define ioremap_uc	ioremap

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

#endif /* __ASM_SH_IO_H */

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