FM / asm

/usr/src/linux-headers-5.15.0-190/arch/sh/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/sh/include/asm

Name	Size	Mode	Actions
adc.h	211	0644	edit dl rm
addrspace.h	1896	0644	edit dl rm
alignment.h	654	0644	edit dl rm
asm-offsets.h	74	0644	edit dl rm
atomic-grb.h	2677	0644	edit dl rm
atomic-irq.h	1687	0644	edit dl rm
atomic-llsc.h	2186	0644	edit dl rm
atomic.h	840	0644	edit dl rm
barrier.h	1503	0644	edit dl rm
bitops-cas.h	1770	0644	edit dl rm
bitops-grb.h	6364	0644	edit dl rm
bitops-llsc.h	2858	0644	edit dl rm
bitops-op32.h	3842	0644	edit dl rm
bitops.h	1653	0644	edit dl rm
bl_bit.h	66	0644	edit dl rm
bl_bit_32.h	639	0644	edit dl rm
bug.h	2835	0644	edit dl rm
cache.h	1171	0644	edit dl rm
cacheflush.h	3735	0644	edit dl rm
cache_insns.h	71	0644	edit dl rm
cache_insns_32.h	642	0644	edit dl rm
checksum.h	68	0644	edit dl rm
checksum_32.h	5009	0644	edit dl rm
clock.h	436	0644	edit dl rm
cmpxchg-cas.h	549	0644	edit dl rm
cmpxchg-grb.h	2869	0644	edit dl rm
cmpxchg-irq.h	1065	0644	edit dl rm
cmpxchg-llsc.h	1085	0644	edit dl rm
cmpxchg-xchg.h	1274	0644	edit dl rm
cmpxchg.h	1822	0644	edit dl rm
device.h	442	0644	edit dl rm
dma-register.h	1708	0644	edit dl rm
dma.h	3652	0644	edit dl rm
dmabrg.h	536	0644	edit dl rm
dwarf.h	9896	0644	edit dl rm
elf.h	6009	0644	edit dl rm
entry-macros.S	1897	0644	edit dl rm
extable.h	135	0644	edit dl rm
fb.h	414	0644	edit dl rm
fixmap.h	2543	0644	edit dl rm
flat.h	863	0644	edit dl rm
fpu.h	1635	0644	edit dl rm
freq.h	212	0644	edit dl rm
ftrace.h	1138	0644	edit dl rm
futex-cas.h	728	0644	edit dl rm
futex-irq.h	482	0644	edit dl rm
futex-llsc.h	870	0644	edit dl rm
futex.h	1381	0644	edit dl rm
gpio.h	851	0644	edit dl rm
hardirq.h	267	0644	edit dl rm
hd64461.h	12068	0644	edit dl rm
heartbeat.h	383	0644	edit dl rm
hugetlb.h	915	0644	edit dl rm
hw_breakpoint.h	1970	0644	edit dl rm
hw_irq.h	915	0644	edit dl rm
i2c-sh7760.h	406	0644	edit dl rm
io.h	8699	0644	edit dl rm
io_generic.h	661	0644	edit dl rm
io_noioport.h	1502	0644	edit dl rm
io_trapped.h	1474	0644	edit dl rm
irq.h	1642	0644	edit dl rm
irqflags.h	226	0644	edit dl rm
Kbuild	141	0644	edit dl rm
kdebug.h	433	0644	edit dl rm
kexec.h	2672	0644	edit dl rm
kgdb.h	851	0644	edit dl rm
kprobes.h	1407	0644	edit dl rm
linkage.h	154	0644	edit dl rm
machvec.h	850	0644	edit dl rm
mmiowb.h	246	0644	edit dl rm
mmu.h	2231	0644	edit dl rm
mmu_context.h	4167	0644	edit dl rm
mmu_context_32.h	1136	0644	edit dl rm
mmzone.h	1052	0644	edit dl rm
module.h	276	0644	edit dl rm
page.h	5419	0644	edit dl rm
pci.h	3007	0644	edit dl rm
perf_event.h	797	0644	edit dl rm
pgalloc.h	1107	0644	edit dl rm
pgtable-2level.h	567	0644	edit dl rm
pgtable-3level.h	1464	0644	edit dl rm
pgtable.h	4305	0644	edit dl rm
pgtable_32.h	15899	0644	edit dl rm
platform_early.h	1850	0644	edit dl rm
posix_types.h	71	0644	edit dl rm
processor.h	4342	0644	edit dl rm
processor_32.h	4614	0644	edit dl rm
ptrace.h	3834	0644	edit dl rm
ptrace_32.h	307	0644	edit dl rm
push-switch.h	755	0644	edit dl rm
reboot.h	472	0644	edit dl rm
romimage-macros.h	1126	0644	edit dl rm
rtc.h	249	0644	edit dl rm
seccomp.h	546	0644	edit dl rm
sections.h	311	0644	edit dl rm
segment.h	860	0644	edit dl rm
setup.h	725	0644	edit dl rm
sfp-machine.h	2767	0644	edit dl rm
sh7760fb.h	5740	0644	edit dl rm
shmparam.h	489	0644	edit dl rm
sh_bios.h	743	0644	edit dl rm
siu.h	385	0644	edit dl rm
smc37c93x.h	5698	0644	edit dl rm
smp-ops.h	1012	0644	edit dl rm
smp.h	1847	0644	edit dl rm
sparsemem.h	319	0644	edit dl rm
spi.h	265	0644	edit dl rm
spinlock-cas.h	2001	0644	edit dl rm
spinlock-llsc.h	4149	0644	edit dl rm
spinlock.h	438	0644	edit dl rm
spinlock_types.h	463	0644	edit dl rm
sram.h	670	0644	edit dl rm
stackprotector.h	711	0644	edit dl rm
stacktrace.h	528	0644	edit dl rm
string.h	66	0644	edit dl rm
string_32.h	2208	0644	edit dl rm
suspend.h	2576	0644	edit dl rm
switch_to.h	190	0644	edit dl rm
switch_to_32.h	3631	0644	edit dl rm
syscall.h	201	0644	edit dl rm
syscalls.h	454	0644	edit dl rm
syscalls_32.h	979	0644	edit dl rm
syscall_32.h	1917	0644	edit dl rm
thread_info.h	5342	0644	edit dl rm
timex.h	637	0644	edit dl rm
tlb.h	625	0644	edit dl rm
tlbflush.h	1809	0644	edit dl rm
topology.h	645	0644	edit dl rm
traps.h	424	0644	edit dl rm
traps_32.h	1338	0644	edit dl rm
types.h	326	0644	edit dl rm
uaccess.h	4811	0644	edit dl rm
uaccess_32.h	5007	0644	edit dl rm
uncached.h	1372	0644	edit dl rm
unistd.h	919	0644	edit dl rm
unwinder.h	856	0644	edit dl rm
user.h	2440	0644	edit dl rm
vermagic.h	709	0644	edit dl rm
vga.h	137	0644	edit dl rm
vmalloc.h	84	0644	edit dl rm
vmlinux.lds.h	416	0644	edit dl rm
watchdog.h	3981	0644	edit dl rm
word-at-a-time.h	1321	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/sh/include/asm/watchdog.h (3981B)

/* SPDX-License-Identifier: GPL-2.0+
 *
 * include/asm-sh/watchdog.h
 *
 * Copyright (C) 2002, 2003 Paul Mundt
 * Copyright (C) 2009 Siemens AG
 * Copyright (C) 2009 Valentin Sitdikov
 */
#ifndef __ASM_SH_WATCHDOG_H
#define __ASM_SH_WATCHDOG_H

#include <linux/types.h>
#include <linux/io.h>

#define WTCNT_HIGH	0x5a
#define WTCSR_HIGH	0xa5

#define WTCSR_CKS2	0x04
#define WTCSR_CKS1	0x02
#define WTCSR_CKS0	0x01

#include <cpu/watchdog.h>

/*
 * See cpu-sh2/watchdog.h for explanation of this stupidity..
 */
#ifndef WTCNT_R
#  define WTCNT_R	WTCNT
#endif

#ifndef WTCSR_R
#  define WTCSR_R	WTCSR
#endif

/*
 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
 * something a little more reasonable, and really can't deal with anything
 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
 *
 * Clock Division Ratio         Overflow Period
 * --------------------------------------------
 *     1/32 (initial value)       41 usecs
 *     1/64                       82 usecs
 *     1/128                     164 usecs
 *     1/256                     328 usecs
 *     1/512                     656 usecs
 *     1/1024                   1.31 msecs
 *     1/2048                   2.62 msecs
 *     1/4096                   5.25 msecs
 */
#define WTCSR_CKS_32	0x00
#define WTCSR_CKS_64	0x01
#define WTCSR_CKS_128	0x02
#define WTCSR_CKS_256	0x03
#define WTCSR_CKS_512	0x04
#define WTCSR_CKS_1024	0x05
#define WTCSR_CKS_2048	0x06
#define WTCSR_CKS_4096	0x07

#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
/**
 * 	sh_wdt_read_cnt - Read from Counter
 * 	Reads back the WTCNT value.
 */
static inline __u32 sh_wdt_read_cnt(void)
{
	return __raw_readl(WTCNT_R);
}

/**
 *	sh_wdt_write_cnt - Write to Counter
 *	@val: Value to write
 *
 *	Writes the given value @val to the lower byte of the timer counter.
 *	The upper byte is set manually on each write.
 */
static inline void sh_wdt_write_cnt(__u32 val)
{
	__raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
}

/**
 *	sh_wdt_write_bst - Write to Counter
 *	@val: Value to write
 *
 *	Writes the given value @val to the lower byte of the timer counter.
 *	The upper byte is set manually on each write.
 */
static inline void sh_wdt_write_bst(__u32 val)
{
	__raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
}
/**
 * 	sh_wdt_read_csr - Read from Control/Status Register
 *
 *	Reads back the WTCSR value.
 */
static inline __u32 sh_wdt_read_csr(void)
{
	return __raw_readl(WTCSR_R);
}

/**
 * 	sh_wdt_write_csr - Write to Control/Status Register
 * 	@val: Value to write
 *
 * 	Writes the given value @val to the lower byte of the control/status
 * 	register. The upper byte is set manually on each write.
 */
static inline void sh_wdt_write_csr(__u32 val)
{
	__raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
}
#else
/**
 * 	sh_wdt_read_cnt - Read from Counter
 * 	Reads back the WTCNT value.
 */
static inline __u8 sh_wdt_read_cnt(void)
{
	return __raw_readb(WTCNT_R);
}

/**
 *	sh_wdt_write_cnt - Write to Counter
 *	@val: Value to write
 *
 *	Writes the given value @val to the lower byte of the timer counter.
 *	The upper byte is set manually on each write.
 */
static inline void sh_wdt_write_cnt(__u8 val)
{
	__raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
}

/**
 * 	sh_wdt_read_csr - Read from Control/Status Register
 *
 *	Reads back the WTCSR value.
 */
static inline __u8 sh_wdt_read_csr(void)
{
	return __raw_readb(WTCSR_R);
}

/**
 * 	sh_wdt_write_csr - Write to Control/Status Register
 * 	@val: Value to write
 *
 * 	Writes the given value @val to the lower byte of the control/status
 * 	register. The upper byte is set manually on each write.
 */
static inline void sh_wdt_write_csr(__u8 val)
{
	__raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
}
#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
#endif /* __ASM_SH_WATCHDOG_H */

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