FM / asm

/usr/src/linux-headers-5.15.0-190/arch/sparc/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/sparc/include/asm

Name	Size	Mode	Actions
adi.h	138	0644	edit dl rm
adi_64.h	812	0644	edit dl rm
agp.h	434	0644	edit dl rm
apb.h	1082	0644	edit dl rm
asm-offsets.h	35	0644	edit dl rm
asm-prototypes.h	729	0644	edit dl rm
asm.h	1101	0644	edit dl rm
asmmacro.h	1183	0644	edit dl rm
atomic.h	219	0644	edit dl rm
atomic_32.h	1760	0644	edit dl rm
atomic_64.h	1849	0644	edit dl rm
auxio.h	310	0644	edit dl rm
auxio_32.h	2615	0644	edit dl rm
auxio_64.h	3253	0644	edit dl rm
backoff.h	2756	0644	edit dl rm
barrier.h	223	0644	edit dl rm
barrier_32.h	160	0644	edit dl rm
barrier_64.h	2004	0644	edit dl rm
bbc.h	9996	0644	edit dl rm
bitext.h	631	0644	edit dl rm
bitops.h	219	0644	edit dl rm
bitops_32.h	2853	0644	edit dl rm
bitops_64.h	1675	0644	edit dl rm
btext.h	145	0644	edit dl rm
bug.h	588	0644	edit dl rm
cache.h	630	0644	edit dl rm
cacheflush.h	373	0644	edit dl rm
cacheflush_32.h	1951	0644	edit dl rm
cacheflush_64.h	2557	0644	edit dl rm
cachetlb_32.h	882	0644	edit dl rm
chafsr.h	9710	0644	edit dl rm
checksum.h	331	0644	edit dl rm
checksum_32.h	5791	0644	edit dl rm
checksum_64.h	3855	0644	edit dl rm
chmctrl.h	8096	0644	edit dl rm
clock.h	231	0644	edit dl rm
clocksource.h	407	0644	edit dl rm
cmpxchg.h	223	0644	edit dl rm
cmpxchg_32.h	2483	0644	edit dl rm
cmpxchg_64.h	5288	0644	edit dl rm
compat.h	3890	0644	edit dl rm
compat_signal.h	565	0644	edit dl rm
contregs.h	1941	0644	edit dl rm
cpudata.h	378	0644	edit dl rm
cpudata_32.h	729	0644	edit dl rm
cpudata_64.h	1153	0644	edit dl rm
cpu_type.h	579	0644	edit dl rm
current.h	991	0644	edit dl rm
dcr.h	728	0644	edit dl rm
dcu.h	1520	0644	edit dl rm
delay.h	215	0644	edit dl rm
delay_32.h	907	0644	edit dl rm
delay_64.h	403	0644	edit dl rm
device.h	565	0644	edit dl rm
dma-mapping.h	336	0644	edit dl rm
dma.h	4989	0644	edit dl rm
ebus_dma.h	1098	0644	edit dl rm
ecc.h	4448	0644	edit dl rm
eeprom.h	254	0644	edit dl rm
elf.h	207	0644	edit dl rm
elf_32.h	3267	0644	edit dl rm
elf_64.h	6848	0644	edit dl rm
estate.h	2287	0644	edit dl rm
extable.h	723	0644	edit dl rm
fb.h	680	0644	edit dl rm
fbio.h	2315	0644	edit dl rm
fhc.h	4533	0644	edit dl rm
floppy.h	219	0644	edit dl rm
floppy_32.h	9796	0644	edit dl rm
floppy_64.h	19392	0644	edit dl rm
fpumacro.h	710	0644	edit dl rm
ftrace.h	801	0644	edit dl rm
futex.h	215	0644	edit dl rm
futex_32.h	82	0644	edit dl rm
futex_64.h	2160	0644	edit dl rm
hardirq.h	223	0644	edit dl rm
hardirq_32.h	334	0644	edit dl rm
hardirq_64.h	412	0644	edit dl rm
head.h	211	0644	edit dl rm
head_32.h	2617	0644	edit dl rm
head_64.h	2184	0644	edit dl rm
hibernate.h	421	0644	edit dl rm
highmem.h	1966	0644	edit dl rm
hugetlb.h	1592	0644	edit dl rm
hvtramp.h	782	0644	edit dl rm
hw_irq.h	88	0644	edit dl rm
hypervisor.h	117649	0644	edit dl rm
ide.h	2222	0644	edit dl rm
idprom.h	656	0644	edit dl rm
intr_queue.h	794	0644	edit dl rm
io-unit.h	2469	0644	edit dl rm
io.h	620	0644	edit dl rm
ioctls.h	358	0644	edit dl rm
iommu-common.h	1445	0644	edit dl rm
iommu.h	215	0644	edit dl rm
iommu_32.h	5865	0644	edit dl rm
iommu_64.h	2489	0644	edit dl rm
io_32.h	3430	0644	edit dl rm
io_64.h	11076	0644	edit dl rm
irq.h	207	0644	edit dl rm
irqflags.h	227	0644	edit dl rm
irqflags_32.h	1058	0644	edit dl rm
irqflags_64.h	1952	0644	edit dl rm
irq_32.h	526	0644	edit dl rm
irq_64.h	3105	0644	edit dl rm
jump_label.h	1036	0644	edit dl rm
Kbuild	177	0644	edit dl rm
kdebug.h	219	0644	edit dl rm
kdebug_32.h	2041	0644	edit dl rm
kdebug_64.h	393	0644	edit dl rm
kgdb.h	1014	0644	edit dl rm
kprobes.h	1410	0644	edit dl rm
ldc.h	4475	0644	edit dl rm
leon.h	7844	0644	edit dl rm
leon_amba.h	8280	0644	edit dl rm
leon_pci.h	512	0644	edit dl rm
lsu.h	1062	0644	edit dl rm
machines.h	1540	0644	edit dl rm
mbus.h	2996	0644	edit dl rm
mc146818rtc.h	298	0644	edit dl rm
mc146818rtc_32.h	699	0644	edit dl rm
mc146818rtc_64.h	689	0644	edit dl rm
mdesc.h	3066	0644	edit dl rm
memctrl.h	311	0644	edit dl rm
mman.h	2633	0644	edit dl rm
mmu.h	207	0644	edit dl rm
mmu_32.h	209	0644	edit dl rm
mmu_64.h	3967	0644	edit dl rm
mmu_context.h	239	0644	edit dl rm
mmu_context_32.h	1082	0644	edit dl rm
mmu_context_64.h	5481	0644	edit dl rm
mmzone.h	363	0644	edit dl rm
mxcc.h	4429	0644	edit dl rm
nmi.h	354	0644	edit dl rm
ns87303.h	3299	0644	edit dl rm
obio.h	6410	0644	edit dl rm
openprom.h	7475	0644	edit dl rm
oplib.h	215	0644	edit dl rm
oplib_32.h	6062	0644	edit dl rm
oplib_64.h	8357	0644	edit dl rm
page.h	274	0644	edit dl rm
page_32.h	3826	0644	edit dl rm
page_64.h	4753	0644	edit dl rm
parport.h	5819	0644	edit dl rm
pbm.h	1505	0644	edit dl rm
pci.h	1367	0644	edit dl rm
pcic.h	5904	0644	edit dl rm
pcr.h	1893	0644	edit dl rm
percpu.h	219	0644	edit dl rm
percpu_32.h	168	0644	edit dl rm
percpu_64.h	541	0644	edit dl rm
perf_event.h	802	0644	edit dl rm
pgalloc.h	223	0644	edit dl rm
pgalloc_32.h	1823	0644	edit dl rm
pgalloc_64.h	2764	0644	edit dl rm
pgtable.h	223	0644	edit dl rm
pgtable_32.h	11021	0644	edit dl rm
pgtable_64.h	32369	0644	edit dl rm
pgtsrmmu.h	4879	0644	edit dl rm
pil.h	1109	0644	edit dl rm
processor.h	231	0644	edit dl rm
processor_32.h	2836	0644	edit dl rm
processor_64.h	7577	0644	edit dl rm
prom.h	1776	0644	edit dl rm
psr.h	1414	0644	edit dl rm
ptrace.h	4294	0644	edit dl rm
qrwlock.h	205	0644	edit dl rm
qspinlock.h	215	0644	edit dl rm
ross.h	5655	0644	edit dl rm
sbi.h	3425	0644	edit dl rm
scratchpad.h	547	0644	edit dl rm
seccomp.h	225	0644	edit dl rm
sections.h	289	0644	edit dl rm
setup.h	1552	0644	edit dl rm
sfafsr.h	3216	0644	edit dl rm
sfp-machine.h	239	0644	edit dl rm
sfp-machine_32.h	6954	0644	edit dl rm
sfp-machine_64.h	3178	0644	edit dl rm
shmparam.h	227	0644	edit dl rm
shmparam_32.h	253	0644	edit dl rm
shmparam_64.h	306	0644	edit dl rm
sigcontext.h	2616	0644	edit dl rm
signal.h	351	0644	edit dl rm
smp.h	207	0644	edit dl rm
smp_32.h	3368	0644	edit dl rm
smp_64.h	1791	0644	edit dl rm
sparsemem.h	295	0644	edit dl rm
spinlock.h	227	0644	edit dl rm
spinlock_32.h	4324	0644	edit dl rm
spinlock_64.h	409	0644	edit dl rm
spinlock_types.h	549	0644	edit dl rm
spitfire.h	9967	0644	edit dl rm
stacktrace.h	166	0644	edit dl rm
starfire.h	418	0644	edit dl rm
string.h	1254	0644	edit dl rm
string_32.h	405	0644	edit dl rm
string_64.h	409	0644	edit dl rm
sunbpp.h	3346	0644	edit dl rm
swift.h	3147	0644	edit dl rm
switch_to.h	231	0644	edit dl rm
switch_to_32.h	3616	0644	edit dl rm
switch_to_64.h	2640	0644	edit dl rm
syscall.h	3464	0644	edit dl rm
syscalls.h	299	0644	edit dl rm
termbits.h	198	0644	edit dl rm
termios.h	5063	0644	edit dl rm
thread_info.h	239	0644	edit dl rm
thread_info_32.h	3773	0644	edit dl rm
thread_info_64.h	8195	0644	edit dl rm
timer.h	215	0644	edit dl rm
timer_32.h	1211	0644	edit dl rm
timer_64.h	2448	0644	edit dl rm
timex.h	215	0644	edit dl rm
timex_32.h	266	0644	edit dl rm
timex_64.h	423	0644	edit dl rm
tlb.h	207	0644	edit dl rm
tlbflush.h	227	0644	edit dl rm
tlbflush_32.h	621	0644	edit dl rm
tlbflush_64.h	1776	0644	edit dl rm
tlb_32.h	138	0644	edit dl rm
tlb_64.h	1056	0644	edit dl rm
topology.h	227	0644	edit dl rm
topology_32.h	170	0644	edit dl rm
topology_64.h	1546	0644	edit dl rm
traps.h	577	0644	edit dl rm
trap_block.h	6786	0644	edit dl rm
tsb.h	12457	0644	edit dl rm
tsunami.h	1890	0644	edit dl rm
ttable.h	20827	0644	edit dl rm
turbosparc.h	3866	0644	edit dl rm
uaccess.h	390	0644	edit dl rm
uaccess_32.h	7032	0644	edit dl rm
uaccess_64.h	6142	0644	edit dl rm
unistd.h	1797	0644	edit dl rm
upa.h	3808	0644	edit dl rm
uprobes.h	1304	0644	edit dl rm
user.h	102	0644	edit dl rm
vaddrs.h	2066	0644	edit dl rm
vdso.h	491	0644	edit dl rm
vga.h	964	0644	edit dl rm
viking.h	8341	0644	edit dl rm
vio.h	12097	0644	edit dl rm
visasm.h	1544	0644	edit dl rm
vmalloc.h	93	0644	edit dl rm
vvar.h	1577	0644	edit dl rm
winmacro.h	4767	0644	edit dl rm
xor.h	207	0644	edit dl rm
xor_32.h	7086	0644	edit dl rm
xor_64.h	2156	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/sparc/include/asm/io_64.h (11076B)

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SPARC64_IO_H
#define __SPARC64_IO_H

#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/types.h>

#include <asm/page.h>      /* IO address mapping routines need this */
#include <asm/asi.h>
#include <asm-generic/pci_iomap.h>

/* BIO layer definitions. */
extern unsigned long kern_base, kern_size;

/* __raw_{read,write}{b,w,l,q} uses direct access.
 * Access the memory as big endian bypassing the cache
 * by using ASI_PHYS_BYPASS_EC_E
 */
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	u8 ret;

__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

return ret;
}

#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	u16 ret;

__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

return ret;
}

#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	u32 ret;

__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

return ret;
}

#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	u64 ret;

__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

return ret;
}

#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

#define __raw_writew __raw_writew
static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

#define __raw_writel __raw_writel
static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

/* Memory functions, same as I/O accesses on Ultra.
 * Access memory as little endian bypassing
 * the cache by using ASI_PHYS_BYPASS_EC_E_L
 */
#define readb readb
#define readb_relaxed readb
static inline u8 readb(const volatile void __iomem *addr)
{	u8 ret;

__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	return ret;
}

#define readw readw
#define readw_relaxed readw
static inline u16 readw(const volatile void __iomem *addr)
{	u16 ret;

__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

return ret;
}

#define readl readl
#define readl_relaxed readl
static inline u32 readl(const volatile void __iomem *addr)
{	u32 ret;

__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

return ret;
}

#define readq readq
#define readq_relaxed readq
static inline u64 readq(const volatile void __iomem *addr)
{	u64 ret;

__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

return ret;
}

#define writeb writeb
#define writeb_relaxed writeb
static inline void writeb(u8 b, volatile void __iomem *addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

#define writew writew
#define writew_relaxed writew
static inline void writew(u16 w, volatile void __iomem *addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

#define writel writel
#define writel_relaxed writel
static inline void writel(u32 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

#define writeq writeq
#define writeq_relaxed writeq
static inline void writeq(u64 q, volatile void __iomem *addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

#define inb inb
static inline u8 inb(unsigned long addr)
{
	return readb((volatile void __iomem *)addr);
}

#define inw inw
static inline u16 inw(unsigned long addr)
{
	return readw((volatile void __iomem *)addr);
}

#define inl inl
static inline u32 inl(unsigned long addr)
{
	return readl((volatile void __iomem *)addr);
}

#define outb outb
static inline void outb(u8 b, unsigned long addr)
{
	writeb(b, (volatile void __iomem *)addr);
}

#define outw outw
static inline void outw(u16 w, unsigned long addr)
{
	writew(w, (volatile void __iomem *)addr);
}

#define outl outl
static inline void outl(u32 l, unsigned long addr)
{
	writel(l, (volatile void __iomem *)addr);
}

#define inb_p(__addr) 		inb(__addr)
#define outb_p(__b, __addr)	outb(__b, __addr)
#define inw_p(__addr)		inw(__addr)
#define outw_p(__w, __addr)	outw(__w, __addr)
#define inl_p(__addr)		inl(__addr)
#define outl_p(__l, __addr)	outl(__l, __addr)

void outsb(unsigned long, const void *, unsigned long);
void outsw(unsigned long, const void *, unsigned long);
void outsl(unsigned long, const void *, unsigned long);
void insb(unsigned long, void *, unsigned long);
void insw(unsigned long, void *, unsigned long);
void insl(unsigned long, void *, unsigned long);

static inline void readsb(void __iomem *port, void *buf, unsigned long count)
{
	insb((unsigned long __force)port, buf, count);
}
static inline void readsw(void __iomem *port, void *buf, unsigned long count)
{
	insw((unsigned long __force)port, buf, count);
}

static inline void readsl(void __iomem *port, void *buf, unsigned long count)
{
	insl((unsigned long __force)port, buf, count);
}

static inline void writesb(void __iomem *port, const void *buf, unsigned long count)
{
	outsb((unsigned long __force)port, buf, count);
}

static inline void writesw(void __iomem *port, const void *buf, unsigned long count)
{
	outsw((unsigned long __force)port, buf, count);
}

static inline void writesl(void __iomem *port, const void *buf, unsigned long count)
{
	outsl((unsigned long __force)port, buf, count);
}

#define ioread8_rep(p,d,l)	readsb(p,d,l)
#define ioread16_rep(p,d,l)	readsw(p,d,l)
#define ioread32_rep(p,d,l)	readsl(p,d,l)
#define iowrite8_rep(p,d,l)	writesb(p,d,l)
#define iowrite16_rep(p,d,l)	writesw(p,d,l)
#define iowrite32_rep(p,d,l)	writesl(p,d,l)

/* Valid I/O Space regions are anywhere, because each PCI bus supported
 * can live in an arbitrary area of the physical address range.
 */
#define IO_SPACE_LIMIT 0xffffffffffffffffUL

/* Now, SBUS variants, only difference from PCI is that we do
 * not use little-endian ASIs.
 */
static inline u8 sbus_readb(const volatile void __iomem *addr)
{
	return __raw_readb(addr);
}

static inline u16 sbus_readw(const volatile void __iomem *addr)
{
	return __raw_readw(addr);
}

static inline u32 sbus_readl(const volatile void __iomem *addr)
{
	return __raw_readl(addr);
}

static inline u64 sbus_readq(const volatile void __iomem *addr)
{
	return __raw_readq(addr);
}

static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
{
	__raw_writeb(b, addr);
}

static inline void sbus_writew(u16 w, volatile void __iomem *addr)
{
	__raw_writew(w, addr);
}

static inline void sbus_writel(u32 l, volatile void __iomem *addr)
{
	__raw_writel(l, addr);
}

static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
{
	__raw_writeq(q, addr);
}

static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
	while(n--) {
		sbus_writeb(c, dst);
		dst++;
	}
}

static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
	volatile void __iomem *d = dst;

while (n--) {
		writeb(c, d);
		d++;
	}
}

static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
				      __kernel_size_t n)
{
	char *d = dst;

while (n--) {
		char tmp = sbus_readb(src);
		*d++ = tmp;
		src++;
	}
}

static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
				 __kernel_size_t n)
{
	char *d = dst;

while (n--) {
		char tmp = readb(src);
		*d++ = tmp;
		src++;
	}
}

static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
				    __kernel_size_t n)
{
	const char *s = src;
	volatile void __iomem *d = dst;

while (n--) {
		char tmp = *s++;
		sbus_writeb(tmp, d);
		d++;
	}
}

static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
			       __kernel_size_t n)
{
	const char *s = src;
	volatile void __iomem *d = dst;

while (n--) {
		char tmp = *s++;
		writeb(tmp, d);
		d++;
	}
}

#ifdef __KERNEL__

/* On sparc64 we have the whole physical IO address space accessible
 * using physically addressed loads and stores, so this does nothing.
 */
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
	return (void __iomem *)offset;
}

#define ioremap_uc(X,Y)			ioremap((X),(Y))
#define ioremap_wc(X,Y)			ioremap((X),(Y))
#define ioremap_wt(X,Y)			ioremap((X),(Y))
static inline void __iomem *ioremap_np(unsigned long offset, unsigned long size)
{
	return NULL;
}

static inline void iounmap(volatile void __iomem *addr)
{
}

#define ioread8			readb
#define ioread16		readw
#define ioread16be		__raw_readw
#define ioread32		readl
#define ioread32be		__raw_readl
#define iowrite8		writeb
#define iowrite16		writew
#define iowrite16be		__raw_writew
#define iowrite32		writel
#define iowrite32be		__raw_writel

/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr);
void ioport_unmap(void __iomem *);

/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
void pci_iounmap(struct pci_dev *dev, void __iomem *);

static inline int sbus_can_dma_64bit(void)
{
	return 1;
}
static inline int sbus_can_burst64(void)
{
	return 1;
}
struct device;
void sbus_set_sbus64(struct device *, int);

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

#endif

#endif /* !(__SPARC64_IO_H) */

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