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/usr/src/linux-headers-5.15.0-190/arch/x86/include/uapi/asm/

/usr/src/linux-headers-5.15.0-190/arch/x86/include/uapi/asm

Name	Size	Mode	Actions
a.out.h	756	0644	edit dl rm
auxvec.h	546	0644	edit dl rm
bitsperlong.h	321	0644	edit dl rm
boot.h	338	0644	edit dl rm
bootparam.h	8233	0644	edit dl rm
byteorder.h	200	0644	edit dl rm
debugreg.h	3344	0644	edit dl rm
e820.h	2620	0644	edit dl rm
hwcap2.h	324	0644	edit dl rm
hw_breakpoint.h	69	0644	edit dl rm
ist.h	869	0644	edit dl rm
Kbuild	117	0644	edit dl rm
kvm.h	10858	0644	edit dl rm
kvm_para.h	4315	0644	edit dl rm
kvm_perf.h	388	0644	edit dl rm
ldt.h	1306	0644	edit dl rm
mce.h	1745	0644	edit dl rm
mman.h	1002	0644	edit dl rm
msgbuf.h	1079	0644	edit dl rm
msr.h	361	0644	edit dl rm
mtrr.h	4240	0644	edit dl rm
perf_regs.h	1403	0644	edit dl rm
posix_types.h	250	0644	edit dl rm
posix_types_32.h	765	0644	edit dl rm
posix_types_64.h	609	0644	edit dl rm
posix_types_x32.h	581	0644	edit dl rm
prctl.h	524	0644	edit dl rm
processor-flags.h	6638	0644	edit dl rm
ptrace-abi.h	2037	0644	edit dl rm
ptrace.h	1630	0644	edit dl rm
sembuf.h	1070	0644	edit dl rm
setup.h	6	0644	edit dl rm
sgx.h	5935	0644	edit dl rm
shmbuf.h	1258	0644	edit dl rm
sigcontext.h	9950	0644	edit dl rm
sigcontext32.h	271	0644	edit dl rm
siginfo.h	422	0644	edit dl rm
signal.h	2200	0644	edit dl rm
stat.h	3131	0644	edit dl rm
statfs.h	416	0644	edit dl rm
svm.h	8917	0644	edit dl rm
swab.h	769	0644	edit dl rm
ucontext.h	2117	0644	edit dl rm
unistd.h	664	0644	edit dl rm
vm86.h	3201	0644	edit dl rm
vmx.h	7383	0644	edit dl rm
vsyscall.h	278	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/x86/include/uapi/asm/debugreg.h (3344B)

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _UAPI_ASM_X86_DEBUGREG_H
#define _UAPI_ASM_X86_DEBUGREG_H

/* Indicate the register numbers for a number of the specific
   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */

#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */

/* Define a few things for the status register.  We can use this to determine
   which debugging register was responsible for the trap.  The other bits
   are either reserved or not of interest to us. */

/* Define reserved bits in DR6 which are always set to 1 */
#define DR6_RESERVED	(0xFFFF0FF0)

#define DR_TRAP0	(0x1)		/* db0 */
#define DR_TRAP1	(0x2)		/* db1 */
#define DR_TRAP2	(0x4)		/* db2 */
#define DR_TRAP3	(0x8)		/* db3 */
#define DR_TRAP_BITS	(DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)

#define DR_BUS_LOCK	(0x800)		/* bus_lock */
#define DR_STEP		(0x4000)	/* single-step */
#define DR_SWITCH	(0x8000)	/* task switch */

/* Now define a bunch of things for manipulating the control register.
   The top two bytes of the control register consist of 4 fields of 4
   bits - each field corresponds to one of the four debug registers,
   and indicates what types of access we trap on, and how large the data
   field is that we are looking at */

#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
#define DR_CONTROL_SIZE 4   /* 4 control bits per register */

#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
#define DR_RW_WRITE (0x1)
#define DR_RW_READ (0x3)

#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
#define DR_LEN_2 (0x4)
#define DR_LEN_4 (0xC)
#define DR_LEN_8 (0x8)

/* The low byte to the control register determine which registers are
   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
   that the processor will reset the bit after a task switch and the other
   is global meaning that we have to explicitly reset the bit.  With linux,
   you can use either one, since we explicitly zero the register when we enter
   kernel mode. */

#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
#define DR_LOCAL_ENABLE (0x1)      /* Local enable for reg 0 */
#define DR_GLOBAL_ENABLE (0x2)     /* Global enable for reg 0 */
#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */

#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */

/* The second byte to the control register has a few special things.
   We can slow the instruction pipeline for instructions coming via the
   gdt or the ldt if we want to.  I am not sure why this is an advantage */

#ifdef __i386__
#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
#else
#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
#endif

#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */

/*
 * HW breakpoint additions
 */

#endif /* _UAPI_ASM_X86_DEBUGREG_H */

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