FM / asm

/usr/src/linux-headers-5.15.0-190/arch/xtensa/include/asm/

/usr/src/linux-headers-5.15.0-190/arch/xtensa/include/asm

Name	Size	Mode	Actions
asm-offsets.h	35	0644	edit dl rm
asm-uaccess.h	4180	0644	edit dl rm
asmmacro.h	4763	0644	edit dl rm
atomic.h	7301	0644	edit dl rm
barrier.h	594	0644	edit dl rm
bitops.h	5398	0644	edit dl rm
bootparam.h	1402	0644	edit dl rm
cache.h	1114	0644	edit dl rm
cacheasm.h	3856	0644	edit dl rm
cacheflush.h	5968	0644	edit dl rm
checksum.h	5893	0644	edit dl rm
cmpxchg.h	5684	0644	edit dl rm
coprocessor.h	4623	0644	edit dl rm
core.h	830	0644	edit dl rm
current.h	679	0644	edit dl rm
delay.h	1668	0644	edit dl rm
dma.h	1830	0644	edit dl rm
elf.h	5115	0644	edit dl rm
fixmap.h	1106	0644	edit dl rm
flat.h	440	0644	edit dl rm
ftrace.h	979	0644	edit dl rm
futex.h	3889	0644	edit dl rm
highmem.h	2167	0644	edit dl rm
hw_breakpoint.h	1597	0644	edit dl rm
initialize_mmu.h	5196	0644	edit dl rm
io.h	1959	0644	edit dl rm
irq.h	1127	0644	edit dl rm
irqflags.h	2069	0644	edit dl rm
jump_label.h	1655	0644	edit dl rm
kasan.h	859	0644	edit dl rm
Kbuild	230	0644	edit dl rm
kmem_layout.h	2790	0644	edit dl rm
linkage.h	154	0644	edit dl rm
mmu.h	462	0644	edit dl rm
mmu_context.h	3624	0644	edit dl rm
mxregs.h	1330	0644	edit dl rm
nommu_context.h	156	0644	edit dl rm
page.h	5793	0644	edit dl rm
pci-bridge.h	2170	0644	edit dl rm
pci.h	1302	0644	edit dl rm
perf_event.h	108	0644	edit dl rm
pgalloc.h	1405	0644	edit dl rm
pgtable.h	14470	0644	edit dl rm
platform.h	1528	0644	edit dl rm
processor.h	7705	0644	edit dl rm
ptrace.h	3321	0644	edit dl rm
regs.h	4017	0644	edit dl rm
seccomp.h	287	0644	edit dl rm
serial.h	443	0644	edit dl rm
shmparam.h	561	0644	edit dl rm
signal.h	502	0644	edit dl rm
smp.h	967	0644	edit dl rm
spinlock.h	472	0644	edit dl rm
spinlock_types.h	317	0644	edit dl rm
stackprotector.h	1140	0644	edit dl rm
stacktrace.h	1158	0644	edit dl rm
string.h	3385	0644	edit dl rm
switch_to.h	601	0644	edit dl rm
syscall.h	2140	0644	edit dl rm
sysmem.h	426	0644	edit dl rm
thread_info.h	3965	0644	edit dl rm
timex.h	1440	0644	edit dl rm
tlb.h	475	0644	edit dl rm
tlbflush.h	5620	0644	edit dl rm
traps.h	2779	0644	edit dl rm
uaccess.h	9375	0644	edit dl rm
ucontext.h	540	0644	edit dl rm
unistd.h	370	0644	edit dl rm
vectors.h	3276	0644	edit dl rm
vermagic.h	433	0644	edit dl rm
vmalloc.h	96	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/arch/xtensa/include/asm/coprocessor.h (4623B)

/*
 * include/asm-xtensa/coprocessor.h
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 - 2007 Tensilica Inc.
 */

#ifndef _XTENSA_COPROCESSOR_H
#define _XTENSA_COPROCESSOR_H

#include <variant/tie.h>
#include <asm/core.h>
#include <asm/types.h>

#ifdef __ASSEMBLY__
# include <variant/tie-asm.h>

.macro	xchal_sa_start  a b
	.set .Lxchal_pofs_, 0
	.set .Lxchal_ofs_, 0
.endm

.macro	xchal_sa_align  ptr minofs maxofs ofsalign totalign
	.set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
	.set	.Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
.endm

#define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
		 | XTHAL_SAS_CC \
		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE )

.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
	.if XTREGS_OPT_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm

.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
	.if XTREGS_OPT_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm
#undef _SELECT

.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
	.if XTREGS_USER_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm

.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
	.if XTREGS_USER_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm
#undef _SELECT

#endif	/* __ASSEMBLY__ */

/*
 * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
 *
 * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
 *
 */

#define XTENSA_HAVE_COPROCESSOR(x)					\
	((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
#define XTENSA_HAVE_COPROCESSORS					\
	(XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
#define XTENSA_HAVE_IO_PORT(x)						\
	(XCHAL_CP_PORT_MASK & (1 << (x)))
#define XTENSA_HAVE_IO_PORTS						\
	XCHAL_CP_PORT_MASK

#ifndef __ASSEMBLY__

/*
 * Additional registers.
 * We define three types of additional registers:
 *  ext: extra registers that are used by the compiler
 *  cpn: optional registers that can be used by a user application
 *  cpX: coprocessor registers that can only be used if the corresponding
 *       CPENABLE bit is set.
 */

#define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...)	\
	__REG ## list (cc, abi, type, name, size, align)

#define __REG0(cc,abi,t,name,s,a)	__REG0_ ## cc (abi,name)
#define __REG1(cc,abi,t,name,s,a)	__REG1_ ## cc (name)
#define __REG2(cc,abi,type,...)		__REG2_ ## type (__VA_ARGS__)

#define __REG0_0(abi,name)
#define __REG0_1(abi,name)		__REG0_1 ## abi (name)
#define __REG0_10(name)	__u32 name;
#define __REG0_11(name)	__u32 name;
#define __REG0_12(name)

#define __REG1_0(name)	__u32 name;
#define __REG1_1(name)

#define __REG2_0(n,s,a)	__u32 name;
#define __REG2_1(n,s,a)	unsigned char n[s] __attribute__ ((aligned(a)));
#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));

typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));

#if XTENSA_HAVE_COPROCESSORS

typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
	__attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
	__attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
	__attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
	__attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
	__attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
	__attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
	__attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
	__attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));

extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
extern void coprocessor_flush(struct thread_info*, int);

extern void coprocessor_release_all(struct thread_info*);
extern void coprocessor_flush_all(struct thread_info*);

#endif	/* XTENSA_HAVE_COPROCESSORS */

#endif	/* !__ASSEMBLY__ */
#endif	/* _XTENSA_COPROCESSOR_H */

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