FM / mtd

/usr/src/linux-headers-5.15.0-190/include/linux/mtd/

/usr/src/linux-headers-5.15.0-190/include/linux/mtd

Name	Size	Mode	Actions
bbm.h	4825	0644	edit dl rm
blktrans.h	2682	0644	edit dl rm
cfi.h	10144	0644	edit dl rm
cfi_endian.h	1514	0644	edit dl rm
concat.h	493	0644	edit dl rm
doc2000.h	5505	0644	edit dl rm
flashchip.h	2478	0644	edit dl rm
ftl.h	2551	0644	edit dl rm
gen_probe.h	615	0644	edit dl rm
hyperbus.h	2893	0644	edit dl rm
inftl.h	1599	0644	edit dl rm
jedec.h	1905	0644	edit dl rm
latch-addr-flash.h	716	0644	edit dl rm
lpc32xx_mlc.h	385	0644	edit dl rm
lpc32xx_slc.h	385	0644	edit dl rm
map.h	13016	0644	edit dl rm
mtd.h	22569	0644	edit dl rm
mtdram.h	257	0644	edit dl rm
nand-ecc-sw-bch.h	2117	0644	edit dl rm
nand-ecc-sw-hamming.h	2717	0644	edit dl rm
nand-gpio.h	330	0644	edit dl rm
nand.h	30284	0644	edit dl rm
ndfc.h	2070	0644	edit dl rm
nftl.h	1734	0644	edit dl rm
onenand.h	7974	0644	edit dl rm
onenand_regs.h	7217	0644	edit dl rm
onfi.h	4962	0644	edit dl rm
partitions.h	3946	0644	edit dl rm
pfow.h	4489	0644	edit dl rm
physmap.h	808	0644	edit dl rm
pismo.h	271	0644	edit dl rm
plat-ram.h	668	0644	edit dl rm
platnand.h	2545	0644	edit dl rm
qinfo.h	2530	0644	edit dl rm
rawnand.h	52400	0644	edit dl rm
sharpsl.h	485	0644	edit dl rm
sh_flctl.h	5927	0644	edit dl rm
spear_smi.h	1714	0644	edit dl rm
spi-nor.h	17247	0644	edit dl rm
spinand.h	16220	0644	edit dl rm
super.h	578	0644	edit dl rm
ubi.h	9914	0644	edit dl rm
xip.h	2556	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/include/linux/mtd/ndfc.h (2070B)

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
 *
 *  Info:
 *   Contains defines, datastructures for ndfc nand controller
 */
#ifndef __LINUX_MTD_NDFC_H
#define __LINUX_MTD_NDFC_H

/* NDFC Register definitions */
#define NDFC_CMD		0x00
#define NDFC_ALE		0x04
#define NDFC_DATA		0x08
#define NDFC_ECC		0x10
#define NDFC_BCFG0		0x30
#define NDFC_BCFG1		0x34
#define NDFC_BCFG2		0x38
#define NDFC_BCFG3		0x3c
#define NDFC_CCR		0x40
#define NDFC_STAT		0x44
#define NDFC_HWCTL		0x48
#define NDFC_REVID		0x50

#define NDFC_STAT_IS_READY	0x01000000

#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */

#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */

#define NDFC_MAX_BANKS		4

struct ndfc_controller_settings {
	uint32_t	ccr_settings;
	uint64_t	ndfc_erpn;
};

struct ndfc_chip_settings {
	uint32_t	bank_settings;
};

#endif

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