FM / usb

/usr/src/linux-headers-5.15.0-190/include/linux/usb/

/usr/src/linux-headers-5.15.0-190/include/linux/usb

Name	Size	Mode	Actions
audio-v2.h	14356	0644	edit dl rm
audio-v3.h	14270	0644	edit dl rm
audio.h	1261	0644	edit dl rm
c67x00.h	1867	0644	edit dl rm
ccid.h	787	0644	edit dl rm
cdc-wdm.h	701	0644	edit dl rm
cdc.h	1517	0644	edit dl rm
cdc_ncm.h	5978	0644	edit dl rm
ch9.h	2342	0644	edit dl rm
chipidea.h	3512	0644	edit dl rm
composite.h	26172	0644	edit dl rm
ehci-dbgp.h	2099	0644	edit dl rm
ehci_def.h	8277	0644	edit dl rm
ehci_pdriver.h	2395	0644	edit dl rm
ezusb.h	286	0644	edit dl rm
functionfs.h	151	0644	edit dl rm
gadget.h	37543	0644	edit dl rm
gadget_configfs.h	3014	0644	edit dl rm
g_hid.h	1158	0644	edit dl rm
hcd.h	28343	0644	edit dl rm
input.h	716	0644	edit dl rm
iowarrior.h	1374	0644	edit dl rm
irda.h	3853	0644	edit dl rm
isp116x.h	1160	0644	edit dl rm
isp1301.h	2433	0644	edit dl rm
isp1362.h	1628	0644	edit dl rm
m66592.h	1444	0644	edit dl rm
musb-ux500.h	899	0644	edit dl rm
musb.h	3600	0644	edit dl rm
net2280.h	24120	0644	edit dl rm
of.h	1859	0644	edit dl rm
ohci_pdriver.h	1748	0644	edit dl rm
otg-fsm.h	8823	0644	edit dl rm
otg.h	3158	0644	edit dl rm
pd.h	15254	0644	edit dl rm
pd_ado.h	1191	0644	edit dl rm
pd_bdo.h	555	0644	edit dl rm
pd_ext_sdb.h	698	0644	edit dl rm
pd_vdo.h	16554	0644	edit dl rm
phy.h	8435	0644	edit dl rm
phy_companion.h	1197	0644	edit dl rm
quirks.h	2403	0644	edit dl rm
r8a66597.h	18069	0644	edit dl rm
r8152.h	1102	0644	edit dl rm
renesas_usbhs.h	4303	0644	edit dl rm
rndis_host.h	6080	0644	edit dl rm
role.h	3663	0644	edit dl rm
serial.h	17596	0644	edit dl rm
sl811.h	838	0644	edit dl rm
storage.h	2645	0644	edit dl rm
tcpci.h	6883	0644	edit dl rm
tcpm.h	6614	0644	edit dl rm
tegra_usb_phy.h	2586	0644	edit dl rm
typec.h	9590	0644	edit dl rm
typec_altmode.h	6639	0644	edit dl rm
typec_dp.h	3998	0644	edit dl rm
typec_mux.h	2115	0644	edit dl rm
typec_tbt.h	1774	0644	edit dl rm
uas.h	2121	0644	edit dl rm
ulpi.h	2319	0644	edit dl rm
usb338x.h	7977	0644	edit dl rm
usbnet.h	10825	0644	edit dl rm
usb_phy_generic.h	582	0644	edit dl rm
xhci-dbgp.h	825	0644	edit dl rm

Edit: /usr/src/linux-headers-5.15.0-190/include/linux/usb/ehci_def.h (8277B)

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2001-2002 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __LINUX_USB_EHCI_DEF_H
#define __LINUX_USB_EHCI_DEF_H

#include <linux/usb/ehci-dbgp.h>

/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */

/* Section 2.2 Host Controller Capability Registers */
struct ehci_caps {
	/* these fields are specified as 8 and 16 bit registers,
	 * but some hosts can't perform 8 or 16 bit PCI accesses.
	 * some hosts treat caplength and hciversion as parts of a 32-bit
	 * register, others treat them as two separate registers, this
	 * affects the memory map for big endian controllers.
	 */
	u32		hc_capbase;
#define HC_LENGTH(ehci, p)	(0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
				(ehci_big_endian_capbase(ehci) ? 24 : 0)))
#define HC_VERSION(ehci, p)	(0xffff&((p) >> /* bits 31:16 / offset 02h */ \
				(ehci_big_endian_capbase(ehci) ? 0 : 16)))
	u32		hcs_params;     /* HCSPARAMS - offset 0x4 */
#define HCS_DEBUG_PORT(p)	(((p)>>20)&0xf)	/* bits 23:20, debug port? */
#define HCS_INDICATOR(p)	((p)&(1 << 16))	/* true: has port indicators */
#define HCS_N_CC(p)		(((p)>>12)&0xf)	/* bits 15:12, #companion HCs */
#define HCS_N_PCC(p)		(((p)>>8)&0xf)	/* bits 11:8, ports per CC */
#define HCS_PORTROUTED(p)	((p)&(1 << 7))	/* true: port routing */
#define HCS_PPC(p)		((p)&(1 << 4))	/* true: port power control */
#define HCS_N_PORTS(p)		(((p)>>0)&0xf)	/* bits 3:0, ports on HC */
#define HCS_N_PORTS_MAX		15		/* N_PORTS valid 0x1-0xF */

u32		hcc_params;      /* HCCPARAMS - offset 0x8 */
/* EHCI 1.1 addendum */
#define HCC_32FRAME_PERIODIC_LIST(p)	((p)&(1 << 19))
#define HCC_PER_PORT_CHANGE_EVENT(p)	((p)&(1 << 18))
#define HCC_LPM(p)			((p)&(1 << 17))
#define HCC_HW_PREFETCH(p)		((p)&(1 << 16))

#define HCC_EXT_CAPS(p)		(((p)>>8)&0xff)	/* for pci extended caps */
#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
#define HCC_CANPARK(p)		((p)&(1 << 2))  /* true: can park on async qh */
#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
	u8		portroute[8];	 /* nibbles for routing - offset 0xC */
};

/* Section 2.3 Host Controller Operational Registers */
struct ehci_regs {

/* USBCMD: offset 0x00 */
	u32		command;

/* EHCI 1.1 addendum */
#define CMD_HIRD	(0xf<<24)	/* host initiated resume duration */
#define CMD_PPCEE	(1<<15)		/* per port change event enable */
#define CMD_FSP		(1<<14)		/* fully synchronized prefetch */
#define CMD_ASPE	(1<<13)		/* async schedule prefetch enable */
#define CMD_PSPE	(1<<12)		/* periodic schedule prefetch enable */
/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
#define CMD_PARK	(1<<11)		/* enable "park" on async qh */
#define CMD_PARK_CNT(c)	(((c)>>8)&3)	/* how many transfers to park for */
#define CMD_LRESET	(1<<7)		/* partial reset (no ports, etc) */
#define CMD_IAAD	(1<<6)		/* "doorbell" interrupt async advance */
#define CMD_ASE		(1<<5)		/* async schedule enable */
#define CMD_PSE		(1<<4)		/* periodic schedule enable */
/* 3:2 is periodic frame list size */
#define CMD_RESET	(1<<1)		/* reset HC not bus */
#define CMD_RUN		(1<<0)		/* start/stop HC */

/* USBSTS: offset 0x04 */
	u32		status;
#define STS_PPCE_MASK	(0xff<<16)	/* Per-Port change event 1-16 */
#define STS_ASS		(1<<15)		/* Async Schedule Status */
#define STS_PSS		(1<<14)		/* Periodic Schedule Status */
#define STS_RECL	(1<<13)		/* Reclamation */
#define STS_HALT	(1<<12)		/* Not running (any reason) */
/* some bits reserved */
	/* these STS_* flags are also intr_enable bits (USBINTR) */
#define STS_IAA		(1<<5)		/* Interrupted on async advance */
#define STS_FATAL	(1<<4)		/* such as some PCI access errors */
#define STS_FLR		(1<<3)		/* frame list rolled over */
#define STS_PCD		(1<<2)		/* port change detect */
#define STS_ERR		(1<<1)		/* "error" completion (overflow, ...) */
#define STS_INT		(1<<0)		/* "normal" completion (short, ...) */

/* USBINTR: offset 0x08 */
	u32		intr_enable;

/* FRINDEX: offset 0x0C */
	u32		frame_index;	/* current microframe number */
	/* CTRLDSSEGMENT: offset 0x10 */
	u32		segment;	/* address bits 63:32 if needed */
	/* PERIODICLISTBASE: offset 0x14 */
	u32		frame_list;	/* points to periodic list */
	/* ASYNCLISTADDR: offset 0x18 */
	u32		async_next;	/* address of next async queue head */

u32		reserved1[2];

/* TXFILLTUNING: offset 0x24 */
	u32		txfill_tuning;	/* TX FIFO Tuning register */
#define TXFIFO_DEFAULT	(8<<16)		/* FIFO burst threshold 8 */

u32		reserved2[6];

/* CONFIGFLAG: offset 0x40 */
	u32		configured_flag;
#define FLAG_CF		(1<<0)		/* true: we'll support "high speed" */

union {
		/* PORTSC: offset 0x44 */
		u32	port_status[HCS_N_PORTS_MAX];	/* up to N_PORTS */
/* EHCI 1.1 addendum */
#define PORTSC_SUSPEND_STS_ACK 0
#define PORTSC_SUSPEND_STS_NYET 1
#define PORTSC_SUSPEND_STS_STALL 2
#define PORTSC_SUSPEND_STS_ERR 3

#define PORT_DEV_ADDR	(0x7f<<25)		/* device address */
#define PORT_SSTS	(0x3<<23)		/* suspend status */
/* 31:23 reserved */
#define PORT_WKOC_E	(1<<22)		/* wake on overcurrent (enable) */
#define PORT_WKDISC_E	(1<<21)		/* wake on disconnect (enable) */
#define PORT_WKCONN_E	(1<<20)		/* wake on connect (enable) */
/* 19:16 for port testing */
#define PORT_TEST(x)	(((x)&0xf)<<16)	/* Port Test Control */
#define PORT_TEST_PKT	PORT_TEST(0x4)	/* Port Test Control - packet test */
#define PORT_TEST_FORCE	PORT_TEST(0x5)	/* Port Test Control - force enable */
#define PORT_LED_OFF	(0<<14)
#define PORT_LED_AMBER	(1<<14)
#define PORT_LED_GREEN	(2<<14)
#define PORT_LED_MASK	(3<<14)
#define PORT_OWNER	(1<<13)		/* true: companion hc owns this port */
#define PORT_POWER	(1<<12)		/* true: has power (see PPC) */
#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))	/* USB 1.1 device */
#define PORT_LS_MASK	(3<<10)		/* Link status (SE0, K or J */
/* 9 reserved */
#define PORT_LPM	(1<<9)		/* LPM transaction */
#define PORT_RESET	(1<<8)		/* reset port */
#define PORT_SUSPEND	(1<<7)		/* suspend port */
#define PORT_RESUME	(1<<6)		/* resume it */
#define PORT_OCC	(1<<5)		/* over current change */
#define PORT_OC		(1<<4)		/* over current active */
#define PORT_PEC	(1<<3)		/* port enable change */
#define PORT_PE		(1<<2)		/* port enable */
#define PORT_CSC	(1<<1)		/* connect status change */
#define PORT_CONNECT	(1<<0)		/* device connected */
#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
		struct {
			u32	reserved3[9];
			/* USBMODE: offset 0x68 */
			u32	usbmode;	/* USB Device mode */
		};
#define USBMODE_SDIS	(1<<3)		/* Stream disable */
#define USBMODE_BE	(1<<2)		/* BE/LE endianness select */
#define USBMODE_CM_HC	(3<<0)		/* host controller mode */
#define USBMODE_CM_IDLE	(0<<0)		/* idle state */
	};

/* Moorestown has some non-standard registers, partially due to the fact that
 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
 * PORTSCx
 */
	union {
		struct {
			u32	reserved4;
			/* HOSTPC: offset 0x84 */
			u32	hostpc[HCS_N_PORTS_MAX];
#define HOSTPC_PHCD	(1<<22)		/* Phy clock disable */
#define HOSTPC_PSPD	(3<<25)		/* Port speed detection */
		};

/* Broadcom-proprietary USB_EHCI_INSNREG00 @ 0x80 */
		u32	brcm_insnreg[4];
	};

u32		reserved5[2];

/* USBMODE_EX: offset 0xc8 */
	u32		usbmode_ex;	/* USB Device mode extension */
#define USBMODE_EX_VBPS	(1<<5)		/* VBus Power Select On */
#define USBMODE_EX_HC	(3<<0)		/* host controller mode */
};

#endif /* __LINUX_USB_EHCI_DEF_H */

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